bat_rw.c 5.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. */
  24. #include <common.h>
  25. #include <asm/processor.h>
  26. #include <asm/mmu.h>
  27. #include <asm/io.h>
  28. #ifdef CONFIG_ADDR_MAP
  29. #include <addr_map.h>
  30. #endif
  31. DECLARE_GLOBAL_DATA_PTR;
  32. int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
  33. {
  34. int batn = -1;
  35. sync();
  36. switch (bat) {
  37. case DBAT0:
  38. mtspr (DBAT0L, lower);
  39. mtspr (DBAT0U, upper);
  40. batn = 0;
  41. break;
  42. case IBAT0:
  43. mtspr (IBAT0L, lower);
  44. mtspr (IBAT0U, upper);
  45. break;
  46. case DBAT1:
  47. mtspr (DBAT1L, lower);
  48. mtspr (DBAT1U, upper);
  49. batn = 1;
  50. break;
  51. case IBAT1:
  52. mtspr (IBAT1L, lower);
  53. mtspr (IBAT1U, upper);
  54. break;
  55. case DBAT2:
  56. mtspr (DBAT2L, lower);
  57. mtspr (DBAT2U, upper);
  58. batn = 2;
  59. break;
  60. case IBAT2:
  61. mtspr (IBAT2L, lower);
  62. mtspr (IBAT2U, upper);
  63. break;
  64. case DBAT3:
  65. mtspr (DBAT3L, lower);
  66. mtspr (DBAT3U, upper);
  67. batn = 3;
  68. break;
  69. case IBAT3:
  70. mtspr (IBAT3L, lower);
  71. mtspr (IBAT3U, upper);
  72. break;
  73. #ifdef CONFIG_HIGH_BATS
  74. case DBAT4:
  75. mtspr (DBAT4L, lower);
  76. mtspr (DBAT4U, upper);
  77. batn = 4;
  78. break;
  79. case IBAT4:
  80. mtspr (IBAT4L, lower);
  81. mtspr (IBAT4U, upper);
  82. break;
  83. case DBAT5:
  84. mtspr (DBAT5L, lower);
  85. mtspr (DBAT5U, upper);
  86. batn = 5;
  87. break;
  88. case IBAT5:
  89. mtspr (IBAT5L, lower);
  90. mtspr (IBAT5U, upper);
  91. break;
  92. case DBAT6:
  93. mtspr (DBAT6L, lower);
  94. mtspr (DBAT6U, upper);
  95. batn = 6;
  96. break;
  97. case IBAT6:
  98. mtspr (IBAT6L, lower);
  99. mtspr (IBAT6U, upper);
  100. break;
  101. case DBAT7:
  102. mtspr (DBAT7L, lower);
  103. mtspr (DBAT7U, upper);
  104. batn = 7;
  105. break;
  106. case IBAT7:
  107. mtspr (IBAT7L, lower);
  108. mtspr (IBAT7U, upper);
  109. break;
  110. #endif
  111. default:
  112. return (-1);
  113. }
  114. #ifdef CONFIG_ADDR_MAP
  115. if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
  116. phys_size_t size;
  117. if (!BATU_VALID(upper))
  118. size = 0;
  119. else
  120. size = BATU_SIZE(upper);
  121. addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
  122. size, batn);
  123. }
  124. #endif
  125. sync();
  126. isync();
  127. return (0);
  128. }
  129. int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
  130. {
  131. unsigned long register u;
  132. unsigned long register l;
  133. switch (bat) {
  134. case DBAT0:
  135. l = mfspr (DBAT0L);
  136. u = mfspr (DBAT0U);
  137. break;
  138. case IBAT0:
  139. l = mfspr (IBAT0L);
  140. u = mfspr (IBAT0U);
  141. break;
  142. case DBAT1:
  143. l = mfspr (DBAT1L);
  144. u = mfspr (DBAT1U);
  145. break;
  146. case IBAT1:
  147. l = mfspr (IBAT1L);
  148. u = mfspr (IBAT1U);
  149. break;
  150. case DBAT2:
  151. l = mfspr (DBAT2L);
  152. u = mfspr (DBAT2U);
  153. break;
  154. case IBAT2:
  155. l = mfspr (IBAT2L);
  156. u = mfspr (IBAT2U);
  157. break;
  158. case DBAT3:
  159. l = mfspr (DBAT3L);
  160. u = mfspr (DBAT3U);
  161. break;
  162. case IBAT3:
  163. l = mfspr (IBAT3L);
  164. u = mfspr (IBAT3U);
  165. break;
  166. #ifdef CONFIG_HIGH_BATS
  167. case DBAT4:
  168. l = mfspr (DBAT4L);
  169. u = mfspr (DBAT4U);
  170. break;
  171. case IBAT4:
  172. l = mfspr (IBAT4L);
  173. u = mfspr (IBAT4U);
  174. break;
  175. case DBAT5:
  176. l = mfspr (DBAT5L);
  177. u = mfspr (DBAT5U);
  178. break;
  179. case IBAT5:
  180. l = mfspr (IBAT5L);
  181. u = mfspr (IBAT5U);
  182. break;
  183. case DBAT6:
  184. l = mfspr (DBAT6L);
  185. u = mfspr (DBAT6U);
  186. break;
  187. case IBAT6:
  188. l = mfspr (IBAT6L);
  189. u = mfspr (IBAT6U);
  190. break;
  191. case DBAT7:
  192. l = mfspr (DBAT7L);
  193. u = mfspr (DBAT7U);
  194. break;
  195. case IBAT7:
  196. l = mfspr (IBAT7L);
  197. u = mfspr (IBAT7U);
  198. break;
  199. #endif
  200. default:
  201. return (-1);
  202. }
  203. *upper = u;
  204. *lower = l;
  205. return (0);
  206. }
  207. void print_bats(void)
  208. {
  209. printf("BAT registers:\n");
  210. printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
  211. printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
  212. printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
  213. printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
  214. printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
  215. printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
  216. printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
  217. printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
  218. printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
  219. printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
  220. printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
  221. printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
  222. printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
  223. printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
  224. printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
  225. printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
  226. #ifdef CONFIG_HIGH_BATS
  227. printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
  228. printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
  229. printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
  230. printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
  231. printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
  232. printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
  233. printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
  234. printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
  235. printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
  236. printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
  237. printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
  238. printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
  239. printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
  240. printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
  241. printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
  242. printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
  243. #endif
  244. }