outs.S 1.2 KB

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  1. /*
  2. * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
  3. *
  4. * Copyright 2005-2009 Analog Devices Inc.
  5. * 2005 BuyWays BV
  6. * Bas Vermeulen <bas@buyways.nl>
  7. *
  8. * Licensed under the GPL-2.
  9. */
  10. #include <asm/linkage.h>
  11. .align 2
  12. ENTRY(_outsl)
  13. P0 = R0; /* P0 = port */
  14. P1 = R1; /* P1 = address */
  15. P2 = R2; /* P2 = count */
  16. LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  17. .Llong_loop_s: R0 = [P1++];
  18. .Llong_loop_e: [P0] = R0;
  19. RTS;
  20. ENDPROC(_outsl)
  21. ENTRY(_outsw)
  22. P0 = R0; /* P0 = port */
  23. P1 = R1; /* P1 = address */
  24. P2 = R2; /* P2 = count */
  25. LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  26. .Lword_loop_s: R0 = W[P1++];
  27. .Lword_loop_e: W[P0] = R0;
  28. RTS;
  29. ENDPROC(_outsw)
  30. ENTRY(_outsb)
  31. P0 = R0; /* P0 = port */
  32. P1 = R1; /* P1 = address */
  33. P2 = R2; /* P2 = count */
  34. LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  35. .Lbyte_loop_s: R0 = B[P1++];
  36. .Lbyte_loop_e: B[P0] = R0;
  37. RTS;
  38. ENDPROC(_outsb)
  39. ENTRY(_outsw_8)
  40. P0 = R0; /* P0 = port */
  41. P1 = R1; /* P1 = address */
  42. P2 = R2; /* P2 = count */
  43. LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
  44. .Lword8_loop_s: R1 = B[P1++];
  45. R0 = B[P1++];
  46. R0 = R0 << 8;
  47. R0 = R0 + R1;
  48. .Lword8_loop_e: W[P0] = R0;
  49. RTS;
  50. ENDPROC(_outsw_8)