ins.S 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117
  1. /*
  2. * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
  3. *
  4. * Copyright 2004-2008 Analog Devices Inc.
  5. * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <asm/blackfin.h>
  9. .align 2
  10. #ifdef CONFIG_IPIPE
  11. # define DO_CLI \
  12. [--sp] = rets; \
  13. [--sp] = (P5:0); \
  14. sp += -12; \
  15. call ___ipipe_disable_root_irqs_hw; \
  16. sp += 12; \
  17. (P5:0) = [sp++];
  18. # define CLI_INNER_NOP
  19. #else
  20. # define DO_CLI cli R3;
  21. # define CLI_INNER_NOP nop; nop; nop;
  22. #endif
  23. #ifdef CONFIG_IPIPE
  24. # define DO_STI \
  25. sp += -12; \
  26. call ___ipipe_enable_root_irqs_hw; \
  27. sp += 12; \
  28. 2: rets = [sp++];
  29. #else
  30. # define DO_STI 2: sti R3;
  31. #endif
  32. #ifdef CONFIG_BFIN_INS_LOWOVERHEAD
  33. # define CLI_OUTER DO_CLI;
  34. # define STI_OUTER DO_STI;
  35. # define CLI_INNER 1:
  36. # if ANOMALY_05000416
  37. # define STI_INNER nop; 2: nop;
  38. # else
  39. # define STI_INNER 2:
  40. # endif
  41. #else
  42. # define CLI_OUTER
  43. # define STI_OUTER
  44. # define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
  45. # define STI_INNER DO_STI;
  46. #endif
  47. /*
  48. * Reads on the Blackfin are speculative. In Blackfin terms, this means they
  49. * can be interrupted at any time (even after they have been issued on to the
  50. * external bus), and re-issued after the interrupt occurs.
  51. *
  52. * If a FIFO is sitting on the end of the read, it will see two reads,
  53. * when the core only sees one. The FIFO receives the read which is cancelled,
  54. * and not delivered to the core.
  55. *
  56. * To solve this, interrupts are turned off before reads occur to I/O space.
  57. * There are 3 versions of all these functions
  58. * - turns interrupts off every read (higher overhead, but lower latency)
  59. * - turns interrupts off every loop (low overhead, but longer latency)
  60. * - DMA version, which do not suffer from this issue. DMA versions have
  61. * different name (prefixed by dma_ ), and are located in
  62. * ../kernel/bfin_dma_5xx.c
  63. * Using the dma related functions are recommended for transfering large
  64. * buffers in/out of FIFOs.
  65. */
  66. #define COMMON_INS(func, ops) \
  67. ENTRY(_ins##func) \
  68. P0 = R0; /* P0 = port */ \
  69. CLI_OUTER; /* 3 instructions before first read access */ \
  70. P1 = R1; /* P1 = address */ \
  71. P2 = R2; /* P2 = count */ \
  72. SSYNC; \
  73. \
  74. LSETUP(1f, 2f) LC0 = P2; \
  75. CLI_INNER; \
  76. ops; \
  77. STI_INNER; \
  78. \
  79. STI_OUTER; \
  80. RTS; \
  81. ENDPROC(_ins##func)
  82. COMMON_INS(l, \
  83. R0 = [P0]; \
  84. [P1++] = R0; \
  85. )
  86. COMMON_INS(w, \
  87. R0 = W[P0]; \
  88. W[P1++] = R0; \
  89. )
  90. COMMON_INS(w_8, \
  91. R0 = W[P0]; \
  92. B[P1++] = R0; \
  93. R0 = R0 >> 8; \
  94. B[P1++] = R0; \
  95. )
  96. COMMON_INS(b, \
  97. R0 = B[P0]; \
  98. B[P1++] = R0; \
  99. )
  100. COMMON_INS(l_16, \
  101. R0 = [P0]; \
  102. W[P1++] = R0; \
  103. R0 = R0 >> 16; \
  104. W[P1++] = R0; \
  105. )