tsec.h 19 KB

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  1. /*
  2. * tsec.h
  3. *
  4. * Driver for the Motorola Triple Speed Ethernet Controller
  5. *
  6. * This software may be used and distributed according to the
  7. * terms of the GNU Public License, Version 2, incorporated
  8. * herein by reference.
  9. *
  10. * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
  11. * (C) Copyright 2003, Motorola, Inc.
  12. * maintained by Xianghua Xiao (x.xiao@motorola.com)
  13. * author Andy Fleming
  14. *
  15. */
  16. #ifndef __TSEC_H
  17. #define __TSEC_H
  18. #include <net.h>
  19. #include <config.h>
  20. #define TSEC_SIZE 0x01000
  21. #define TSEC_MDIO_OFFSET 0x01000
  22. #define STD_TSEC_INFO(num) \
  23. { \
  24. .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
  25. .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
  26. .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  27. + (num - 1) * TSEC_MDIO_OFFSET), \
  28. .devname = CONFIG_TSEC##num##_NAME, \
  29. .phyaddr = TSEC##num##_PHY_ADDR, \
  30. .flags = TSEC##num##_FLAGS \
  31. }
  32. #define SET_STD_TSEC_INFO(x, num) \
  33. { \
  34. x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
  35. x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
  36. x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
  37. + (num - 1) * TSEC_MDIO_OFFSET); \
  38. x.devname = CONFIG_TSEC##num##_NAME; \
  39. x.phyaddr = TSEC##num##_PHY_ADDR; \
  40. x.flags = TSEC##num##_FLAGS;\
  41. }
  42. #define MAC_ADDR_LEN 6
  43. /* #define TSEC_TIMEOUT 1000000 */
  44. #define TSEC_TIMEOUT 1000
  45. #define TOUT_LOOP 1000000
  46. #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
  47. /* TBI register addresses */
  48. #define TBI_CR 0x00
  49. #define TBI_SR 0x01
  50. #define TBI_ANA 0x04
  51. #define TBI_ANLPBPA 0x05
  52. #define TBI_ANEX 0x06
  53. #define TBI_TBICON 0x11
  54. /* TBI MDIO register bit fields*/
  55. #define TBICON_CLK_SELECT 0x0020
  56. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  57. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  58. #define TBIANA_HALF_DUPLEX 0x0040
  59. #define TBIANA_FULL_DUPLEX 0x0020
  60. #define TBICR_PHY_RESET 0x8000
  61. #define TBICR_ANEG_ENABLE 0x1000
  62. #define TBICR_RESTART_ANEG 0x0200
  63. #define TBICR_FULL_DUPLEX 0x0100
  64. #define TBICR_SPEED1_SET 0x0040
  65. /* MAC register bits */
  66. #define MACCFG1_SOFT_RESET 0x80000000
  67. #define MACCFG1_RESET_RX_MC 0x00080000
  68. #define MACCFG1_RESET_TX_MC 0x00040000
  69. #define MACCFG1_RESET_RX_FUN 0x00020000
  70. #define MACCFG1_RESET_TX_FUN 0x00010000
  71. #define MACCFG1_LOOPBACK 0x00000100
  72. #define MACCFG1_RX_FLOW 0x00000020
  73. #define MACCFG1_TX_FLOW 0x00000010
  74. #define MACCFG1_SYNCD_RX_EN 0x00000008
  75. #define MACCFG1_RX_EN 0x00000004
  76. #define MACCFG1_SYNCD_TX_EN 0x00000002
  77. #define MACCFG1_TX_EN 0x00000001
  78. #define MACCFG2_INIT_SETTINGS 0x00007205
  79. #define MACCFG2_FULL_DUPLEX 0x00000001
  80. #define MACCFG2_IF 0x00000300
  81. #define MACCFG2_GMII 0x00000200
  82. #define MACCFG2_MII 0x00000100
  83. #define ECNTRL_INIT_SETTINGS 0x00001000
  84. #define ECNTRL_TBI_MODE 0x00000020
  85. #define ECNTRL_R100 0x00000008
  86. #define ECNTRL_SGMII_MODE 0x00000002
  87. #define miim_end -2
  88. #define miim_read -1
  89. #ifndef CONFIG_SYS_TBIPA_VALUE
  90. #define CONFIG_SYS_TBIPA_VALUE 0x1f
  91. #endif
  92. #define MIIMCFG_INIT_VALUE 0x00000003
  93. #define MIIMCFG_RESET 0x80000000
  94. #define MIIMIND_BUSY 0x00000001
  95. #define MIIMIND_NOTVALID 0x00000004
  96. #define MIIM_CONTROL 0x00
  97. #define MIIM_CONTROL_RESET 0x00009140
  98. #define MIIM_CONTROL_INIT 0x00001140
  99. #define MIIM_CONTROL_RESTART 0x00001340
  100. #define MIIM_ANEN 0x00001000
  101. #define MIIM_CR 0x00
  102. #define MIIM_CR_RST 0x00008000
  103. #define MIIM_CR_INIT 0x00001000
  104. #define MIIM_STATUS 0x1
  105. #define MIIM_STATUS_AN_DONE 0x00000020
  106. #define MIIM_STATUS_LINK 0x0004
  107. #define PHY_BMSR_AUTN_ABLE 0x0008
  108. #define PHY_BMSR_AUTN_COMP 0x0020
  109. #define MIIM_PHYIR1 0x2
  110. #define MIIM_PHYIR2 0x3
  111. #define MIIM_ANAR 0x4
  112. #define MIIM_ANAR_INIT 0x1e1
  113. #define MIIM_TBI_ANLPBPA 0x5
  114. #define MIIM_TBI_ANLPBPA_HALF 0x00000040
  115. #define MIIM_TBI_ANLPBPA_FULL 0x00000020
  116. #define MIIM_TBI_ANEX 0x6
  117. #define MIIM_TBI_ANEX_NP 0x00000004
  118. #define MIIM_TBI_ANEX_PRX 0x00000002
  119. #define MIIM_GBIT_CONTROL 0x9
  120. #define MIIM_GBIT_CONTROL_INIT 0xe00
  121. #define MIIM_EXT_PAGE_ACCESS 0x1f
  122. /* Broadcom BCM54xx -- taken from linux sungem_phy */
  123. #define MIIM_BCM54xx_AUXCNTL 0x18
  124. #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
  125. #define MIIM_BCM54xx_AUXSTATUS 0x19
  126. #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
  127. #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
  128. /* Cicada Auxiliary Control/Status Register */
  129. #define MIIM_CIS8201_AUX_CONSTAT 0x1c
  130. #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
  131. #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
  132. #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
  133. #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
  134. #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
  135. /* Cicada Extended Control Register 1 */
  136. #define MIIM_CIS8201_EXT_CON1 0x17
  137. #define MIIM_CIS8201_EXTCON1_INIT 0x0000
  138. /* Cicada 8204 Extended PHY Control Register 1 */
  139. #define MIIM_CIS8204_EPHY_CON 0x17
  140. #define MIIM_CIS8204_EPHYCON_INIT 0x0006
  141. #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
  142. /* Cicada 8204 Serial LED Control Register */
  143. #define MIIM_CIS8204_SLED_CON 0x1b
  144. #define MIIM_CIS8204_SLEDCON_INIT 0x1115
  145. #define MIIM_GBIT_CON 0x09
  146. #define MIIM_GBIT_CON_ADVERT 0x0e00
  147. /* Entry for Vitesse VSC8244 regs starts here */
  148. /* Vitesse VSC8244 Auxiliary Control/Status Register */
  149. #define MIIM_VSC8244_AUX_CONSTAT 0x1c
  150. #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
  151. #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
  152. #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
  153. #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
  154. #define MIIM_VSC8244_AUXCONSTAT_100 0x0008
  155. #define MIIM_CONTROL_INIT_LOOPBACK 0x4000
  156. /* Vitesse VSC8244 Extended PHY Control Register 1 */
  157. #define MIIM_VSC8244_EPHY_CON 0x17
  158. #define MIIM_VSC8244_EPHYCON_INIT 0x0006
  159. /* Vitesse VSC8244 Serial LED Control Register */
  160. #define MIIM_VSC8244_LED_CON 0x1b
  161. #define MIIM_VSC8244_LEDCON_INIT 0xF011
  162. /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
  163. /* Vitesse VSC8601 Extended PHY Control Register 1 */
  164. #define MIIM_VSC8601_EPHY_CON 0x17
  165. #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
  166. #define MIIM_VSC8601_SKEW_CTRL 0x1c
  167. /* 88E1011 PHY Status Register */
  168. #define MIIM_88E1011_PHY_STATUS 0x11
  169. #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
  170. #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
  171. #define MIIM_88E1011_PHYSTAT_100 0x4000
  172. #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
  173. #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
  174. #define MIIM_88E1011_PHYSTAT_LINK 0x0400
  175. #define MIIM_88E1011_PHY_SCR 0x10
  176. #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
  177. /* 88E1111 PHY LED Control Register */
  178. #define MIIM_88E1111_PHY_LED_CONTROL 24
  179. #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
  180. #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
  181. /* 88E1121 PHY LED Control Register */
  182. #define MIIM_88E1121_PHY_LED_CTRL 16
  183. #define MIIM_88E1121_PHY_LED_PAGE 3
  184. #define MIIM_88E1121_PHY_LED_DEF 0x0030
  185. /* 88E1121 PHY IRQ Enable/Status Register */
  186. #define MIIM_88E1121_PHY_IRQ_EN 18
  187. #define MIIM_88E1121_PHY_IRQ_STATUS 19
  188. #define MIIM_88E1121_PHY_PAGE 22
  189. /* 88E1145 Extended PHY Specific Control Register */
  190. #define MIIM_88E1145_PHY_EXT_CR 20
  191. #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
  192. #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
  193. #define MIIM_88E1145_PHY_PAGE 29
  194. #define MIIM_88E1145_PHY_CAL_OV 30
  195. /* RTL8211B PHY Status Register */
  196. #define MIIM_RTL8211B_PHY_STATUS 0x11
  197. #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
  198. #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
  199. #define MIIM_RTL8211B_PHYSTAT_100 0x4000
  200. #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
  201. #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
  202. #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
  203. /* DM9161 Control register values */
  204. #define MIIM_DM9161_CR_STOP 0x0400
  205. #define MIIM_DM9161_CR_RSTAN 0x1200
  206. #define MIIM_DM9161_SCR 0x10
  207. #define MIIM_DM9161_SCR_INIT 0x0610
  208. /* DM9161 Specified Configuration and Status Register */
  209. #define MIIM_DM9161_SCSR 0x11
  210. #define MIIM_DM9161_SCSR_100F 0x8000
  211. #define MIIM_DM9161_SCSR_100H 0x4000
  212. #define MIIM_DM9161_SCSR_10F 0x2000
  213. #define MIIM_DM9161_SCSR_10H 0x1000
  214. /* DM9161 10BT Configuration/Status */
  215. #define MIIM_DM9161_10BTCSR 0x12
  216. #define MIIM_DM9161_10BTCSR_INIT 0x7800
  217. /* LXT971 Status 2 registers */
  218. #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
  219. #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
  220. #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
  221. #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
  222. #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
  223. #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
  224. /* DP83865 Control register values */
  225. #define MIIM_DP83865_CR_INIT 0x9200
  226. /* DP83865 Link and Auto-Neg Status Register */
  227. #define MIIM_DP83865_LANR 0x11
  228. #define MIIM_DP83865_SPD_MASK 0x0018
  229. #define MIIM_DP83865_SPD_1000 0x0010
  230. #define MIIM_DP83865_SPD_100 0x0008
  231. #define MIIM_DP83865_DPX_FULL 0x0002
  232. #define MIIM_READ_COMMAND 0x00000001
  233. #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
  234. #define MINFLR_INIT_SETTINGS 0x00000040
  235. #define DMACTRL_INIT_SETTINGS 0x000000c3
  236. #define DMACTRL_GRS 0x00000010
  237. #define DMACTRL_GTS 0x00000008
  238. #define TSTAT_CLEAR_THALT 0x80000000
  239. #define RSTAT_CLEAR_RHALT 0x00800000
  240. #define IEVENT_INIT_CLEAR 0xffffffff
  241. #define IEVENT_BABR 0x80000000
  242. #define IEVENT_RXC 0x40000000
  243. #define IEVENT_BSY 0x20000000
  244. #define IEVENT_EBERR 0x10000000
  245. #define IEVENT_MSRO 0x04000000
  246. #define IEVENT_GTSC 0x02000000
  247. #define IEVENT_BABT 0x01000000
  248. #define IEVENT_TXC 0x00800000
  249. #define IEVENT_TXE 0x00400000
  250. #define IEVENT_TXB 0x00200000
  251. #define IEVENT_TXF 0x00100000
  252. #define IEVENT_IE 0x00080000
  253. #define IEVENT_LC 0x00040000
  254. #define IEVENT_CRL 0x00020000
  255. #define IEVENT_XFUN 0x00010000
  256. #define IEVENT_RXB0 0x00008000
  257. #define IEVENT_GRSC 0x00000100
  258. #define IEVENT_RXF0 0x00000080
  259. #define IMASK_INIT_CLEAR 0x00000000
  260. #define IMASK_TXEEN 0x00400000
  261. #define IMASK_TXBEN 0x00200000
  262. #define IMASK_TXFEN 0x00100000
  263. #define IMASK_RXFEN0 0x00000080
  264. /* Default Attribute fields */
  265. #define ATTR_INIT_SETTINGS 0x000000c0
  266. #define ATTRELI_INIT_SETTINGS 0x00000000
  267. /* TxBD status field bits */
  268. #define TXBD_READY 0x8000
  269. #define TXBD_PADCRC 0x4000
  270. #define TXBD_WRAP 0x2000
  271. #define TXBD_INTERRUPT 0x1000
  272. #define TXBD_LAST 0x0800
  273. #define TXBD_CRC 0x0400
  274. #define TXBD_DEF 0x0200
  275. #define TXBD_HUGEFRAME 0x0080
  276. #define TXBD_LATECOLLISION 0x0080
  277. #define TXBD_RETRYLIMIT 0x0040
  278. #define TXBD_RETRYCOUNTMASK 0x003c
  279. #define TXBD_UNDERRUN 0x0002
  280. #define TXBD_STATS 0x03ff
  281. /* RxBD status field bits */
  282. #define RXBD_EMPTY 0x8000
  283. #define RXBD_RO1 0x4000
  284. #define RXBD_WRAP 0x2000
  285. #define RXBD_INTERRUPT 0x1000
  286. #define RXBD_LAST 0x0800
  287. #define RXBD_FIRST 0x0400
  288. #define RXBD_MISS 0x0100
  289. #define RXBD_BROADCAST 0x0080
  290. #define RXBD_MULTICAST 0x0040
  291. #define RXBD_LARGE 0x0020
  292. #define RXBD_NONOCTET 0x0010
  293. #define RXBD_SHORT 0x0008
  294. #define RXBD_CRCERR 0x0004
  295. #define RXBD_OVERRUN 0x0002
  296. #define RXBD_TRUNCATED 0x0001
  297. #define RXBD_STATS 0x003f
  298. typedef struct txbd8
  299. {
  300. ushort status; /* Status Fields */
  301. ushort length; /* Buffer length */
  302. uint bufPtr; /* Buffer Pointer */
  303. } txbd8_t;
  304. typedef struct rxbd8
  305. {
  306. ushort status; /* Status Fields */
  307. ushort length; /* Buffer Length */
  308. uint bufPtr; /* Buffer Pointer */
  309. } rxbd8_t;
  310. typedef struct rmon_mib
  311. {
  312. /* Transmit and Receive Counters */
  313. uint tr64; /* Transmit and Receive 64-byte Frame Counter */
  314. uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
  315. uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
  316. uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
  317. uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
  318. uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
  319. uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
  320. /* Receive Counters */
  321. uint rbyt; /* Receive Byte Counter */
  322. uint rpkt; /* Receive Packet Counter */
  323. uint rfcs; /* Receive FCS Error Counter */
  324. uint rmca; /* Receive Multicast Packet (Counter) */
  325. uint rbca; /* Receive Broadcast Packet */
  326. uint rxcf; /* Receive Control Frame Packet */
  327. uint rxpf; /* Receive Pause Frame Packet */
  328. uint rxuo; /* Receive Unknown OP Code */
  329. uint raln; /* Receive Alignment Error */
  330. uint rflr; /* Receive Frame Length Error */
  331. uint rcde; /* Receive Code Error */
  332. uint rcse; /* Receive Carrier Sense Error */
  333. uint rund; /* Receive Undersize Packet */
  334. uint rovr; /* Receive Oversize Packet */
  335. uint rfrg; /* Receive Fragments */
  336. uint rjbr; /* Receive Jabber */
  337. uint rdrp; /* Receive Drop */
  338. /* Transmit Counters */
  339. uint tbyt; /* Transmit Byte Counter */
  340. uint tpkt; /* Transmit Packet */
  341. uint tmca; /* Transmit Multicast Packet */
  342. uint tbca; /* Transmit Broadcast Packet */
  343. uint txpf; /* Transmit Pause Control Frame */
  344. uint tdfr; /* Transmit Deferral Packet */
  345. uint tedf; /* Transmit Excessive Deferral Packet */
  346. uint tscl; /* Transmit Single Collision Packet */
  347. /* (0x2_n700) */
  348. uint tmcl; /* Transmit Multiple Collision Packet */
  349. uint tlcl; /* Transmit Late Collision Packet */
  350. uint txcl; /* Transmit Excessive Collision Packet */
  351. uint tncl; /* Transmit Total Collision */
  352. uint res2;
  353. uint tdrp; /* Transmit Drop Frame */
  354. uint tjbr; /* Transmit Jabber Frame */
  355. uint tfcs; /* Transmit FCS Error */
  356. uint txcf; /* Transmit Control Frame */
  357. uint tovr; /* Transmit Oversize Frame */
  358. uint tund; /* Transmit Undersize Frame */
  359. uint tfrg; /* Transmit Fragments Frame */
  360. /* General Registers */
  361. uint car1; /* Carry Register One */
  362. uint car2; /* Carry Register Two */
  363. uint cam1; /* Carry Register One Mask */
  364. uint cam2; /* Carry Register Two Mask */
  365. } rmon_mib_t;
  366. typedef struct tsec_hash_regs
  367. {
  368. uint iaddr0; /* Individual Address Register 0 */
  369. uint iaddr1; /* Individual Address Register 1 */
  370. uint iaddr2; /* Individual Address Register 2 */
  371. uint iaddr3; /* Individual Address Register 3 */
  372. uint iaddr4; /* Individual Address Register 4 */
  373. uint iaddr5; /* Individual Address Register 5 */
  374. uint iaddr6; /* Individual Address Register 6 */
  375. uint iaddr7; /* Individual Address Register 7 */
  376. uint res1[24];
  377. uint gaddr0; /* Group Address Register 0 */
  378. uint gaddr1; /* Group Address Register 1 */
  379. uint gaddr2; /* Group Address Register 2 */
  380. uint gaddr3; /* Group Address Register 3 */
  381. uint gaddr4; /* Group Address Register 4 */
  382. uint gaddr5; /* Group Address Register 5 */
  383. uint gaddr6; /* Group Address Register 6 */
  384. uint gaddr7; /* Group Address Register 7 */
  385. uint res2[24];
  386. } tsec_hash_t;
  387. typedef struct tsec_mdio {
  388. uint res1[4];
  389. uint ieventm;
  390. uint imaskm;
  391. uint res2;
  392. uint emapm;
  393. uint res3[320];
  394. uint miimcfg; /* MII Management: Configuration */
  395. uint miimcom; /* MII Management: Command */
  396. uint miimadd; /* MII Management: Address */
  397. uint miimcon; /* MII Management: Control */
  398. uint miimstat; /* MII Management: Status */
  399. uint miimind; /* MII Management: Indicators */
  400. uint res4[690];
  401. } tsec_mdio_t;
  402. typedef struct tsec
  403. {
  404. /* General Control and Status Registers (0x2_n000) */
  405. uint res000[4];
  406. uint ievent; /* Interrupt Event */
  407. uint imask; /* Interrupt Mask */
  408. uint edis; /* Error Disabled */
  409. uint res01c;
  410. uint ecntrl; /* Ethernet Control */
  411. uint minflr; /* Minimum Frame Length */
  412. uint ptv; /* Pause Time Value */
  413. uint dmactrl; /* DMA Control */
  414. uint tbipa; /* TBI PHY Address */
  415. uint res034[3];
  416. uint res040[48];
  417. /* Transmit Control and Status Registers (0x2_n100) */
  418. uint tctrl; /* Transmit Control */
  419. uint tstat; /* Transmit Status */
  420. uint res108;
  421. uint tbdlen; /* Tx BD Data Length */
  422. uint res110[5];
  423. uint ctbptr; /* Current TxBD Pointer */
  424. uint res128[23];
  425. uint tbptr; /* TxBD Pointer */
  426. uint res188[30];
  427. /* (0x2_n200) */
  428. uint res200;
  429. uint tbase; /* TxBD Base Address */
  430. uint res208[42];
  431. uint ostbd; /* Out of Sequence TxBD */
  432. uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
  433. uint res2b8[18];
  434. /* Receive Control and Status Registers (0x2_n300) */
  435. uint rctrl; /* Receive Control */
  436. uint rstat; /* Receive Status */
  437. uint res308;
  438. uint rbdlen; /* RxBD Data Length */
  439. uint res310[4];
  440. uint res320;
  441. uint crbptr; /* Current Receive Buffer Pointer */
  442. uint res328[6];
  443. uint mrblr; /* Maximum Receive Buffer Length */
  444. uint res344[16];
  445. uint rbptr; /* RxBD Pointer */
  446. uint res388[30];
  447. /* (0x2_n400) */
  448. uint res400;
  449. uint rbase; /* RxBD Base Address */
  450. uint res408[62];
  451. /* MAC Registers (0x2_n500) */
  452. uint maccfg1; /* MAC Configuration #1 */
  453. uint maccfg2; /* MAC Configuration #2 */
  454. uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
  455. uint hafdup; /* Half-duplex */
  456. uint maxfrm; /* Maximum Frame */
  457. uint res514;
  458. uint res518;
  459. uint res51c;
  460. uint resmdio[6];
  461. uint res538;
  462. uint ifstat; /* Interface Status */
  463. uint macstnaddr1; /* Station Address, part 1 */
  464. uint macstnaddr2; /* Station Address, part 2 */
  465. uint res548[46];
  466. /* (0x2_n600) */
  467. uint res600[32];
  468. /* RMON MIB Registers (0x2_n680-0x2_n73c) */
  469. rmon_mib_t rmon;
  470. uint res740[48];
  471. /* Hash Function Registers (0x2_n800) */
  472. tsec_hash_t hash;
  473. uint res900[128];
  474. /* Pattern Registers (0x2_nb00) */
  475. uint resb00[62];
  476. uint attr; /* Default Attribute Register */
  477. uint attreli; /* Default Attribute Extract Length and Index */
  478. /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
  479. uint resc00[256];
  480. } tsec_t;
  481. #define TSEC_GIGABIT (1)
  482. /* This flag currently only has
  483. * meaning if we're using the eTSEC */
  484. #define TSEC_REDUCED (1 << 1)
  485. #define TSEC_SGMII (1 << 2)
  486. struct tsec_private {
  487. volatile tsec_t *regs;
  488. volatile tsec_mdio_t *phyregs;
  489. volatile tsec_mdio_t *phyregs_sgmii;
  490. struct phy_info *phyinfo;
  491. uint phyaddr;
  492. u32 flags;
  493. uint link;
  494. uint duplexity;
  495. uint speed;
  496. };
  497. /*
  498. * struct phy_cmd: A command for reading or writing a PHY register
  499. *
  500. * mii_reg: The register to read or write
  501. *
  502. * mii_data: For writes, the value to put in the register.
  503. * A value of -1 indicates this is a read.
  504. *
  505. * funct: A function pointer which is invoked for each command.
  506. * For reads, this function will be passed the value read
  507. * from the PHY, and process it.
  508. * For writes, the result of this function will be written
  509. * to the PHY register
  510. */
  511. struct phy_cmd {
  512. uint mii_reg;
  513. uint mii_data;
  514. uint (*funct) (uint mii_reg, struct tsec_private * priv);
  515. };
  516. /* struct phy_info: a structure which defines attributes for a PHY
  517. *
  518. * id will contain a number which represents the PHY. During
  519. * startup, the driver will poll the PHY to find out what its
  520. * UID--as defined by registers 2 and 3--is. The 32-bit result
  521. * gotten from the PHY will be shifted right by "shift" bits to
  522. * discard any bits which may change based on revision numbers
  523. * unimportant to functionality
  524. *
  525. * The struct phy_cmd entries represent pointers to an arrays of
  526. * commands which tell the driver what to do to the PHY.
  527. */
  528. struct phy_info {
  529. uint id;
  530. char *name;
  531. uint shift;
  532. /* Called to configure the PHY, and modify the controller
  533. * based on the results */
  534. struct phy_cmd *config;
  535. /* Called when starting up the controller */
  536. struct phy_cmd *startup;
  537. /* Called when bringing down the controller */
  538. struct phy_cmd *shutdown;
  539. };
  540. struct tsec_info_struct {
  541. tsec_t *regs;
  542. tsec_mdio_t *miiregs;
  543. tsec_mdio_t *miiregs_sgmii;
  544. char *devname;
  545. unsigned int phyaddr;
  546. u32 flags;
  547. };
  548. int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
  549. int tsec_standard_init(bd_t *bis);
  550. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
  551. #endif /* __TSEC_H */