sym53c8xx.h 18 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Denis Peter, MPL AG Switzerland
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. *
  24. * Most of these definitions are derived from
  25. * linux/drivers/scsi/sym53c8xx_defs.h
  26. *
  27. */
  28. #ifndef _SYM53C8XX_DEFS_H
  29. #define _SYM53C8XX_DEFS_H
  30. #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
  31. #define SCNTL1 0x01 /* no reset */
  32. #define ISCON 0x10 /* connected to scsi */
  33. #define CRST 0x08 /* force reset */
  34. #define IARB 0x02 /* immediate arbitration */
  35. #define SCNTL2 0x02 /* no disconnect expected */
  36. #define SDU 0x80 /* cmd: disconnect will raise error */
  37. #define CHM 0x40 /* sta: chained mode */
  38. #define WSS 0x08 /* sta: wide scsi send [W]*/
  39. #define WSR 0x01 /* sta: wide scsi received [W]*/
  40. #define SCNTL3 0x03 /* cnf system clock dependent */
  41. #define EWS 0x08 /* cmd: enable wide scsi [W]*/
  42. #define ULTRA 0x80 /* cmd: ULTRA enable */
  43. /* bits 0-2, 7 rsvd for C1010 */
  44. #define SCID 0x04 /* cnf host adapter scsi address */
  45. #define RRE 0x40 /* r/w:e enable response to resel. */
  46. #define SRE 0x20 /* r/w:e enable response to select */
  47. #define SXFER 0x05 /* ### Sync speed and count */
  48. /* bits 6-7 rsvd for C1010 */
  49. #define SDID 0x06 /* ### Destination-ID */
  50. #define GPREG 0x07 /* ??? IO-Pins */
  51. #define SFBR 0x08 /* ### First byte in phase */
  52. #define SOCL 0x09
  53. #define CREQ 0x80 /* r/w: SCSI-REQ */
  54. #define CACK 0x40 /* r/w: SCSI-ACK */
  55. #define CBSY 0x20 /* r/w: SCSI-BSY */
  56. #define CSEL 0x10 /* r/w: SCSI-SEL */
  57. #define CATN 0x08 /* r/w: SCSI-ATN */
  58. #define CMSG 0x04 /* r/w: SCSI-MSG */
  59. #define CC_D 0x02 /* r/w: SCSI-C_D */
  60. #define CI_O 0x01 /* r/w: SCSI-I_O */
  61. #define SSID 0x0a
  62. #define SBCL 0x0b
  63. #define DSTAT 0x0c
  64. #define DFE 0x80 /* sta: dma fifo empty */
  65. #define MDPE 0x40 /* int: master data parity error */
  66. #define BF 0x20 /* int: script: bus fault */
  67. #define ABRT 0x10 /* int: script: command aborted */
  68. #define SSI 0x08 /* int: script: single step */
  69. #define SIR 0x04 /* int: script: interrupt instruct. */
  70. #define IID 0x01 /* int: script: illegal instruct. */
  71. #define SSTAT0 0x0d
  72. #define ILF 0x80 /* sta: data in SIDL register lsb */
  73. #define ORF 0x40 /* sta: data in SODR register lsb */
  74. #define OLF 0x20 /* sta: data in SODL register lsb */
  75. #define AIP 0x10 /* sta: arbitration in progress */
  76. #define LOA 0x08 /* sta: arbitration lost */
  77. #define WOA 0x04 /* sta: arbitration won */
  78. #define IRST 0x02 /* sta: scsi reset signal */
  79. #define SDP 0x01 /* sta: scsi parity signal */
  80. #define SSTAT1 0x0e
  81. #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
  82. #define SSTAT2 0x0f
  83. #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
  84. #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
  85. #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
  86. #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
  87. #define LDSC 0x02 /* sta: disconnect & reconnect */
  88. #define DSA 0x10 /* --> Base page */
  89. #define DSA1 0x11
  90. #define DSA2 0x12
  91. #define DSA3 0x13
  92. #define ISTAT 0x14 /* --> Main Command and status */
  93. #define CABRT 0x80 /* cmd: abort current operation */
  94. #define SRST 0x40 /* mod: reset chip */
  95. #define SIGP 0x20 /* r/w: message from host to ncr */
  96. #define SEM 0x10 /* r/w: message between host + ncr */
  97. #define CON 0x08 /* sta: connected to scsi */
  98. #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
  99. #define SIP 0x02 /* sta: scsi-interrupt */
  100. #define DIP 0x01 /* sta: host/script interrupt */
  101. #define CTEST0 0x18
  102. #define CTEST1 0x19
  103. #define CTEST2 0x1a
  104. #define CSIGP 0x40
  105. /* bits 0-2,7 rsvd for C1010 */
  106. #define CTEST3 0x1b
  107. #define FLF 0x08 /* cmd: flush dma fifo */
  108. #define CLF 0x04 /* cmd: clear dma fifo */
  109. #define FM 0x02 /* mod: fetch pin mode */
  110. #define WRIE 0x01 /* mod: write and invalidate enable */
  111. /* bits 4-7 rsvd for C1010 */
  112. #define DFIFO 0x20
  113. #define CTEST4 0x21
  114. #define BDIS 0x80 /* mod: burst disable */
  115. #define MPEE 0x08 /* mod: master parity error enable */
  116. #define CTEST5 0x22
  117. #define DFS 0x20 /* mod: dma fifo size */
  118. /* bits 0-1, 3-7 rsvd for C1010 */
  119. #define CTEST6 0x23
  120. #define DBC 0x24 /* ### Byte count and command */
  121. #define DNAD 0x28 /* ### Next command register */
  122. #define DSP 0x2c /* --> Script Pointer */
  123. #define DSPS 0x30 /* --> Script pointer save/opcode#2 */
  124. #define SCRATCHA 0x34 /* Temporary register a */
  125. #define SCRATCHA1 0x35
  126. #define SCRATCHA2 0x36
  127. #define SCRATCHA3 0x37
  128. #define DMODE 0x38
  129. #define BL_2 0x80 /* mod: burst length shift value +2 */
  130. #define BL_1 0x40 /* mod: burst length shift value +1 */
  131. #define ERL 0x08 /* mod: enable read line */
  132. #define ERMP 0x04 /* mod: enable read multiple */
  133. #define BOF 0x02 /* mod: burst op code fetch */
  134. #define MAN 0x01 /* mod: manual start */
  135. #define DIEN 0x39
  136. #define SBR 0x3a
  137. #define DCNTL 0x3b /* --> Script execution control */
  138. #define CLSE 0x80 /* mod: cache line size enable */
  139. #define PFF 0x40 /* cmd: pre-fetch flush */
  140. #define PFEN 0x20 /* mod: pre-fetch enable */
  141. #define SSM 0x10 /* mod: single step mode */
  142. #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
  143. #define STD 0x04 /* cmd: start dma mode */
  144. #define IRQD 0x02 /* mod: irq disable */
  145. #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
  146. /* bits 0-1 rsvd for C1010 */
  147. #define ADDER 0x3c
  148. #define SIEN 0x40 /* -->: interrupt enable */
  149. #define SIST 0x42 /* <--: interrupt status */
  150. #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
  151. #define STO 0x0400/* sta: timeout (select) */
  152. #define GEN 0x0200/* sta: timeout (general) */
  153. #define HTH 0x0100/* sta: timeout (handshake) */
  154. #define MA 0x80 /* sta: phase mismatch */
  155. #define CMP 0x40 /* sta: arbitration complete */
  156. #define SEL 0x20 /* sta: selected by another device */
  157. #define RSL 0x10 /* sta: reselected by another device*/
  158. #define SGE 0x08 /* sta: gross error (over/underflow)*/
  159. #define UDC 0x04 /* sta: unexpected disconnect */
  160. #define RST 0x02 /* sta: scsi bus reset detected */
  161. #define PAR 0x01 /* sta: scsi parity error */
  162. #define SLPAR 0x44
  163. #define SWIDE 0x45
  164. #define MACNTL 0x46
  165. #define GPCNTL 0x47
  166. #define STIME0 0x48 /* cmd: timeout for select&handshake*/
  167. #define STIME1 0x49 /* cmd: timeout user defined */
  168. #define RESPID 0x4a /* sta: Reselect-IDs */
  169. #define STEST0 0x4c
  170. #define STEST1 0x4d
  171. #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
  172. #define DBLEN 0x08 /* clock doubler running */
  173. #define DBLSEL 0x04 /* clock doubler selected */
  174. #define STEST2 0x4e
  175. #define ROF 0x40 /* reset scsi offset (after gross error!) */
  176. #define EXT 0x02 /* extended filtering */
  177. #define STEST3 0x4f
  178. #define TE 0x80 /* c: tolerAnt enable */
  179. #define HSC 0x20 /* c: Halt SCSI Clock */
  180. #define CSF 0x02 /* c: clear scsi fifo */
  181. #define SIDL 0x50 /* Lowlevel: latched from scsi data */
  182. #define STEST4 0x52
  183. #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
  184. #define SMODE_HVD 0x40 /* High Voltage Differential */
  185. #define SMODE_SE 0x80 /* Single Ended */
  186. #define SMODE_LVD 0xc0 /* Low Voltage Differential */
  187. #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
  188. /* bits 0-5 rsvd for C1010 */
  189. #define SODL 0x54 /* Lowlevel: data out to scsi data */
  190. #define SBDL 0x58 /* Lowlevel: data from scsi data */
  191. /*-----------------------------------------------------------
  192. **
  193. ** Utility macros for the script.
  194. **
  195. **-----------------------------------------------------------
  196. */
  197. #define REG(r) (r)
  198. /*-----------------------------------------------------------
  199. **
  200. ** SCSI phases
  201. **
  202. ** DT phases illegal for ncr driver.
  203. **
  204. **-----------------------------------------------------------
  205. */
  206. #define SCR_DATA_OUT 0x00000000
  207. #define SCR_DATA_IN 0x01000000
  208. #define SCR_COMMAND 0x02000000
  209. #define SCR_STATUS 0x03000000
  210. #define SCR_DT_DATA_OUT 0x04000000
  211. #define SCR_DT_DATA_IN 0x05000000
  212. #define SCR_MSG_OUT 0x06000000
  213. #define SCR_MSG_IN 0x07000000
  214. #define SCR_ILG_OUT 0x04000000
  215. #define SCR_ILG_IN 0x05000000
  216. /*-----------------------------------------------------------
  217. **
  218. ** Data transfer via SCSI.
  219. **
  220. **-----------------------------------------------------------
  221. **
  222. ** MOVE_ABS (LEN)
  223. ** <<start address>>
  224. **
  225. ** MOVE_IND (LEN)
  226. ** <<dnad_offset>>
  227. **
  228. ** MOVE_TBL
  229. ** <<dnad_offset>>
  230. **
  231. **-----------------------------------------------------------
  232. */
  233. #define OPC_MOVE 0x08000000
  234. #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
  235. #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
  236. #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
  237. #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
  238. #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
  239. #define SCR_CHMOV_TBL (0x10000000)
  240. /*-----------------------------------------------------------
  241. **
  242. ** Selection
  243. **
  244. **-----------------------------------------------------------
  245. **
  246. ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
  247. ** <<alternate_address>>
  248. **
  249. ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
  250. ** <<alternate_address>>
  251. **
  252. **-----------------------------------------------------------
  253. */
  254. #define SCR_SEL_ABS 0x40000000
  255. #define SCR_SEL_ABS_ATN 0x41000000
  256. #define SCR_SEL_TBL 0x42000000
  257. #define SCR_SEL_TBL_ATN 0x43000000
  258. #define SCR_JMP_REL 0x04000000
  259. #define SCR_ID(id) (((unsigned long)(id)) << 16)
  260. /*-----------------------------------------------------------
  261. **
  262. ** Waiting for Disconnect or Reselect
  263. **
  264. **-----------------------------------------------------------
  265. **
  266. ** WAIT_DISC
  267. ** dummy: <<alternate_address>>
  268. **
  269. ** WAIT_RESEL
  270. ** <<alternate_address>>
  271. **
  272. **-----------------------------------------------------------
  273. */
  274. #define SCR_WAIT_DISC 0x48000000
  275. #define SCR_WAIT_RESEL 0x50000000
  276. /*-----------------------------------------------------------
  277. **
  278. ** Bit Set / Reset
  279. **
  280. **-----------------------------------------------------------
  281. **
  282. ** SET (flags {|.. })
  283. **
  284. ** CLR (flags {|.. })
  285. **
  286. **-----------------------------------------------------------
  287. */
  288. #define SCR_SET(f) (0x58000000 | (f))
  289. #define SCR_CLR(f) (0x60000000 | (f))
  290. #define SCR_CARRY 0x00000400
  291. #define SCR_TRG 0x00000200
  292. #define SCR_ACK 0x00000040
  293. #define SCR_ATN 0x00000008
  294. /*-----------------------------------------------------------
  295. **
  296. ** Memory to memory move
  297. **
  298. **-----------------------------------------------------------
  299. **
  300. ** COPY (bytecount)
  301. ** << source_address >>
  302. ** << destination_address >>
  303. **
  304. ** SCR_COPY sets the NO FLUSH option by default.
  305. ** SCR_COPY_F does not set this option.
  306. **
  307. ** For chips which do not support this option,
  308. ** ncr_copy_and_bind() will remove this bit.
  309. **-----------------------------------------------------------
  310. */
  311. #define SCR_NO_FLUSH 0x01000000
  312. #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
  313. #define SCR_COPY_F(n) (0xc0000000 | (n))
  314. /*-----------------------------------------------------------
  315. **
  316. ** Register move and binary operations
  317. **
  318. **-----------------------------------------------------------
  319. **
  320. ** SFBR_REG (reg, op, data) reg = SFBR op data
  321. ** << 0 >>
  322. **
  323. ** REG_SFBR (reg, op, data) SFBR = reg op data
  324. ** << 0 >>
  325. **
  326. ** REG_REG (reg, op, data) reg = reg op data
  327. ** << 0 >>
  328. **
  329. **-----------------------------------------------------------
  330. ** On 810A, 860, 825A, 875, 895 and 896 chips the content
  331. ** of SFBR register can be used as data (SCR_SFBR_DATA).
  332. ** The 896 has additionnal IO registers starting at
  333. ** offset 0x80. Bit 7 of register offset is stored in
  334. ** bit 7 of the SCRIPTS instruction first DWORD.
  335. **-----------------------------------------------------------
  336. */
  337. #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
  338. #define SCR_SFBR_REG(reg,op,data) \
  339. (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  340. #define SCR_REG_SFBR(reg,op,data) \
  341. (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  342. #define SCR_REG_REG(reg,op,data) \
  343. (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  344. #define SCR_LOAD 0x00000000
  345. #define SCR_SHL 0x01000000
  346. #define SCR_OR 0x02000000
  347. #define SCR_XOR 0x03000000
  348. #define SCR_AND 0x04000000
  349. #define SCR_SHR 0x05000000
  350. #define SCR_ADD 0x06000000
  351. #define SCR_ADDC 0x07000000
  352. #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
  353. /*-----------------------------------------------------------
  354. **
  355. ** FROM_REG (reg) SFBR = reg
  356. ** << 0 >>
  357. **
  358. ** TO_REG (reg) reg = SFBR
  359. ** << 0 >>
  360. **
  361. ** LOAD_REG (reg, data) reg = <data>
  362. ** << 0 >>
  363. **
  364. ** LOAD_SFBR(data) SFBR = <data>
  365. ** << 0 >>
  366. **
  367. **-----------------------------------------------------------
  368. */
  369. #define SCR_FROM_REG(reg) \
  370. SCR_REG_SFBR(reg,SCR_OR,0)
  371. #define SCR_TO_REG(reg) \
  372. SCR_SFBR_REG(reg,SCR_OR,0)
  373. #define SCR_LOAD_REG(reg,data) \
  374. SCR_REG_REG(reg,SCR_LOAD,data)
  375. #define SCR_LOAD_SFBR(data) \
  376. (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
  377. /*-----------------------------------------------------------
  378. **
  379. ** LOAD from memory to register.
  380. ** STORE from register to memory.
  381. **
  382. ** Only supported by 810A, 860, 825A, 875, 895 and 896.
  383. **
  384. **-----------------------------------------------------------
  385. **
  386. ** LOAD_ABS (LEN)
  387. ** <<start address>>
  388. **
  389. ** LOAD_REL (LEN) (DSA relative)
  390. ** <<dsa_offset>>
  391. **
  392. **-----------------------------------------------------------
  393. */
  394. #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
  395. #define SCR_NO_FLUSH2 0x02000000
  396. #define SCR_DSA_REL2 0x10000000
  397. #define SCR_LOAD_R(reg, how, n) \
  398. (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  399. #define SCR_STORE_R(reg, how, n) \
  400. (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  401. #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
  402. #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
  403. #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
  404. #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
  405. #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
  406. #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
  407. #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
  408. #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
  409. /*-----------------------------------------------------------
  410. **
  411. ** Waiting for Disconnect or Reselect
  412. **
  413. **-----------------------------------------------------------
  414. **
  415. ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
  416. ** <<address>>
  417. **
  418. ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
  419. ** <<distance>>
  420. **
  421. ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
  422. ** <<address>>
  423. **
  424. ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
  425. ** <<distance>>
  426. **
  427. ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
  428. ** <<dummy>>
  429. **
  430. ** INT [ | IFTRUE/IFFALSE ( ... ) ]
  431. ** <<ident>>
  432. **
  433. ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
  434. ** <<ident>>
  435. **
  436. ** Conditions:
  437. ** WHEN (phase)
  438. ** IF (phase)
  439. ** CARRYSET
  440. ** DATA (data, mask)
  441. **
  442. **-----------------------------------------------------------
  443. */
  444. #define SCR_NO_OP 0x80000000
  445. #define SCR_JUMP 0x80080000
  446. #define SCR_JUMP64 0x80480000
  447. #define SCR_JUMPR 0x80880000
  448. #define SCR_CALL 0x88080000
  449. #define SCR_CALLR 0x88880000
  450. #define SCR_RETURN 0x90080000
  451. #define SCR_INT 0x98080000
  452. #define SCR_INT_FLY 0x98180000
  453. #define IFFALSE(arg) (0x00080000 | (arg))
  454. #define IFTRUE(arg) (0x00000000 | (arg))
  455. #define WHEN(phase) (0x00030000 | (phase))
  456. #define IF(phase) (0x00020000 | (phase))
  457. #define DATA(D) (0x00040000 | ((D) & 0xff))
  458. #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
  459. #define CARRYSET (0x00200000)
  460. #define SIR_COMPLETE 0x10000000
  461. /* script errors */
  462. #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
  463. #define SIR_CMD_OUT_ILL_PH 0x00000002
  464. #define SIR_STATUS_ILL_PH 0x00000003
  465. #define SIR_MSG_RECEIVED 0x00000004
  466. #define SIR_DATA_IN_ERR 0x00000005
  467. #define SIR_DATA_OUT_ERR 0x00000006
  468. #define SIR_SCRIPT_ERROR 0x00000007
  469. #define SIR_MSG_OUT_NO_CMD 0x00000008
  470. #define SIR_MSG_OVER7 0x00000009
  471. /* Fly interrupt */
  472. #define INT_ON_FY 0x00000080
  473. /* Hardware errors are defined in scsi.h */
  474. #define SCSI_IDENTIFY 0xC0
  475. #ifndef TRUE
  476. #define TRUE 1
  477. #endif
  478. #ifndef FALSE
  479. #define FALSE 0
  480. #endif
  481. #endif