ppc4xx_enet.h 19 KB

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  1. /*----------------------------------------------------------------------------+
  2. | This source code is dual-licensed. You may use it under the terms of the
  3. | GNU General Public License version 2, or under the license below.
  4. |
  5. | This source code has been made available to you by IBM on an AS-IS
  6. | basis. Anyone receiving this source is licensed under IBM
  7. | copyrights to use it in any way he or she deems fit, including
  8. | copying it, modifying it, compiling it, and redistributing it either
  9. | with or without modifications. No license under IBM patents or
  10. | patent applications is to be implied by the copyright license.
  11. |
  12. | Any user of this software should understand that IBM cannot provide
  13. | technical support for this software and will not be responsible for
  14. | any consequences resulting from the use of this software.
  15. |
  16. | Any person who transfers this source code or any derivative work
  17. | must include the IBM copyright notice, this paragraph, and the
  18. | preceding two paragraphs in the transferred software.
  19. |
  20. | COPYRIGHT I B M CORPORATION 1999
  21. | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  22. +----------------------------------------------------------------------------*/
  23. /*----------------------------------------------------------------------------+
  24. |
  25. | File Name: enetemac.h
  26. |
  27. | Function: Header file for the EMAC3 macro on the 405GP.
  28. |
  29. | Author: Mark Wisner
  30. |
  31. | Change Activity-
  32. |
  33. | Date Description of Change BY
  34. | --------- --------------------- ---
  35. | 29-Apr-99 Created MKW
  36. |
  37. +----------------------------------------------------------------------------*/
  38. /*----------------------------------------------------------------------------+
  39. | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  40. | ported to handle 440GP and 440GX multiple EMACs
  41. +----------------------------------------------------------------------------*/
  42. #ifndef _PPC4XX_ENET_H_
  43. #define _PPC4XX_ENET_H_
  44. #include <net.h>
  45. #include "405_mal.h"
  46. /*-----------------------------------------------------------------------------+
  47. | General enternet defines. 802 frames are not supported.
  48. +-----------------------------------------------------------------------------*/
  49. #define ENET_ADDR_LENGTH 6
  50. #define ENET_ARPTYPE 0x806
  51. #define ARP_REQUEST 1
  52. #define ARP_REPLY 2
  53. #define ENET_IPTYPE 0x800
  54. #define ARP_CACHE_SIZE 5
  55. #define NUM_TX_BUFF 1
  56. #define NUM_RX_BUFF PKTBUFSRX
  57. struct enet_frame {
  58. unsigned char dest_addr[ENET_ADDR_LENGTH];
  59. unsigned char source_addr[ENET_ADDR_LENGTH];
  60. unsigned short type;
  61. unsigned char enet_data[1];
  62. };
  63. struct arp_entry {
  64. unsigned long inet_address;
  65. unsigned char mac_address[ENET_ADDR_LENGTH];
  66. unsigned long valid;
  67. unsigned long sec;
  68. unsigned long nsec;
  69. };
  70. /* Statistic Areas */
  71. #define MAX_ERR_LOG 10
  72. typedef struct emac_stats_st{ /* Statistic Block */
  73. int data_len_err;
  74. int rx_frames;
  75. int rx;
  76. int rx_prot_err;
  77. int int_err;
  78. int pkts_tx;
  79. int pkts_rx;
  80. int pkts_handled;
  81. short tx_err_log[MAX_ERR_LOG];
  82. short rx_err_log[MAX_ERR_LOG];
  83. } EMAC_STATS_ST, *EMAC_STATS_PST;
  84. /* Structure containing variables used by the shared code (4xx_enet.c) */
  85. typedef struct emac_4xx_hw_st {
  86. uint32_t hw_addr; /* EMAC offset */
  87. uint32_t tah_addr; /* TAH offset */
  88. uint32_t phy_id;
  89. uint32_t phy_addr;
  90. uint32_t original_fc;
  91. uint32_t txcw;
  92. uint32_t autoneg_failed;
  93. uint32_t emac_ier;
  94. volatile mal_desc_t *tx;
  95. volatile mal_desc_t *rx;
  96. u32 tx_phys;
  97. u32 rx_phys;
  98. bd_t *bis; /* for eth_init upon mal error */
  99. mal_desc_t *alloc_tx_buf;
  100. mal_desc_t *alloc_rx_buf;
  101. char *txbuf_ptr;
  102. uint16_t devnum;
  103. int get_link_status;
  104. int tbi_compatibility_en;
  105. int tbi_compatibility_on;
  106. int fc_send_xon;
  107. int report_tx_early;
  108. int first_init;
  109. int tx_err_index;
  110. int rx_err_index;
  111. int rx_slot; /* MAL Receive Slot */
  112. int rx_i_index; /* Receive Interrupt Queue Index */
  113. int rx_u_index; /* Receive User Queue Index */
  114. int tx_slot; /* MAL Transmit Slot */
  115. int tx_i_index; /* Transmit Interrupt Queue Index */
  116. int tx_u_index; /* Transmit User Queue Index */
  117. int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
  118. int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
  119. int is_receiving; /* sync with eth interrupt */
  120. int print_speed; /* print speed message upon start */
  121. EMAC_STATS_ST stats;
  122. } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
  123. #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
  124. #define EMAC_NUM_DEV 4
  125. #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
  126. defined(CONFIG_NET_MULTI) && \
  127. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
  128. #define EMAC_NUM_DEV 2
  129. #else
  130. #define EMAC_NUM_DEV 1
  131. #endif
  132. #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
  133. #define EMAC_STACR_OC_MASK (0x00008000)
  134. #else
  135. #define EMAC_STACR_OC_MASK (0x00000000)
  136. #endif
  137. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  138. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  139. defined(CONFIG_405EX)
  140. #define SDR0_PFC1_EM_1000 (0x00200000)
  141. #endif
  142. /*
  143. * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
  144. * not have a pin function control (PFC) register to otherwise determine
  145. * the bridge configuration.
  146. */
  147. #define EMAC_PHY_MODE_NONE 0
  148. #define EMAC_PHY_MODE_NONE_RGMII 1
  149. #define EMAC_PHY_MODE_RGMII_NONE 2
  150. #define EMAC_PHY_MODE_RGMII_RGMII 3
  151. #define EMAC_PHY_MODE_NONE_GMII 4
  152. #define EMAC_PHY_MODE_GMII_NONE 5
  153. #define EMAC_PHY_MODE_NONE_MII 6
  154. #define EMAC_PHY_MODE_MII_NONE 7
  155. /* ZMII Bridge Register addresses */
  156. #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  157. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  158. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  159. #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
  160. #else
  161. #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
  162. #endif
  163. #define ZMII0_FER (ZMII0_BASE)
  164. #define ZMII0_SSR (ZMII0_BASE + 4)
  165. #define ZMII0_SMIISR (ZMII0_BASE + 8)
  166. /* ZMII FER Register Bit Definitions */
  167. #define ZMII_FER_DIS (0x0)
  168. #define ZMII_FER_MDI (0x8)
  169. #define ZMII_FER_SMII (0x4)
  170. #define ZMII_FER_RMII (0x2)
  171. #define ZMII_FER_MII (0x1)
  172. #define ZMII_FER_RSVD11 (0x00200000)
  173. #define ZMII_FER_RSVD10 (0x00100000)
  174. #define ZMII_FER_RSVD14_31 (0x0003FFFF)
  175. #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
  176. /* ZMII Speed Selection Register Bit Definitions */
  177. #define ZMII0_SSR_SCI (0x4)
  178. #define ZMII0_SSR_FSS (0x2)
  179. #define ZMII0_SSR_SP (0x1)
  180. #define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
  181. #define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
  182. /* ZMII SMII Status Register Bit Definitions */
  183. #define ZMII0_SMIISR_E1 (0x80)
  184. #define ZMII0_SMIISR_EC (0x40)
  185. #define ZMII0_SMIISR_EN (0x20)
  186. #define ZMII0_SMIISR_EJ (0x10)
  187. #define ZMII0_SMIISR_EL (0x08)
  188. #define ZMII0_SMIISR_ED (0x04)
  189. #define ZMII0_SMIISR_ES (0x02)
  190. #define ZMII0_SMIISR_EF (0x01)
  191. #define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
  192. /* RGMII Register Addresses */
  193. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  194. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
  195. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  196. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
  197. #elif defined(CONFIG_405EX)
  198. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
  199. #else
  200. #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
  201. #endif
  202. #define RGMII_FER (RGMII_BASE + 0x00)
  203. #define RGMII_SSR (RGMII_BASE + 0x04)
  204. #if defined(CONFIG_460GT)
  205. #define RGMII1_BASE_OFFSET 0x100
  206. #endif
  207. /* RGMII Function Enable (FER) Register Bit Definitions */
  208. #define RGMII_FER_DIS (0x00)
  209. #define RGMII_FER_RTBI (0x04)
  210. #define RGMII_FER_RGMII (0x05)
  211. #define RGMII_FER_TBI (0x06)
  212. #define RGMII_FER_GMII (0x07)
  213. #define RGMII_FER_MII (RGMII_FER_GMII)
  214. #define RGMII_FER_V(__x) ((__x - 2) * 4)
  215. #define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
  216. /* RGMII Speed Selection Register Bit Definitions */
  217. #define RGMII_SSR_SP_10MBPS (0x00)
  218. #define RGMII_SSR_SP_100MBPS (0x02)
  219. #define RGMII_SSR_SP_1000MBPS (0x04)
  220. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  221. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  222. defined(CONFIG_405EX)
  223. #define RGMII_SSR_V(__x) ((__x) * 8)
  224. #else
  225. #define RGMII_SSR_V(__x) ((__x -2) * 8)
  226. #endif
  227. /*---------------------------------------------------------------------------+
  228. | TCP/IP Acceleration Hardware (TAH) 440GX Only
  229. +---------------------------------------------------------------------------*/
  230. #if defined(CONFIG_440GX)
  231. #define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
  232. #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
  233. #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
  234. #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
  235. #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
  236. #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
  237. #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
  238. #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
  239. #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
  240. #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
  241. /* TAH Revision */
  242. #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
  243. #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
  244. #define TAH_REV_RN_V (8)
  245. #define TAH_REV_BN_V (0)
  246. /* TAH Mode Register */
  247. #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
  248. #define TAH_MR_SR (0x40000000) /* Software reset */
  249. #define TAH_MR_ST (0x3F000000) /* Send Threshold */
  250. #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
  251. #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
  252. #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
  253. #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
  254. #define TAH_MR_ST_V (20)
  255. #define TAH_MR_TFS_V (17)
  256. #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
  257. #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
  258. #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
  259. #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
  260. #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
  261. /* TAH Segment Size Registers 0:5 */
  262. #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
  263. #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
  264. #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
  265. /* TAH Transmit Status Register */
  266. #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
  267. #define TAH_TSR_UH (0x40000000) /* Unrecognized header */
  268. #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
  269. #define TAH_TSR_IPOP (0x10000000) /* IP option present */
  270. #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
  271. #define TAH_TSR_ILTS (0x04000000) /* IP length too short */
  272. #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
  273. #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
  274. #define TAH_TSR_TFP (0x00800000) /* TCP flags present */
  275. #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
  276. #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
  277. #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
  278. #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
  279. #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
  280. #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
  281. #endif /* CONFIG_440GX */
  282. /* Ethernet MAC Regsiter Addresses */
  283. #if defined(CONFIG_440)
  284. #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  285. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  286. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  287. #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
  288. #else
  289. #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
  290. #endif
  291. #else
  292. #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
  293. #define EMAC0_BASE 0xEF600900
  294. #else
  295. #define EMAC0_BASE 0xEF600800
  296. #endif
  297. #endif
  298. #if defined(CONFIG_440EPX)
  299. #define EMAC1_BASE 0xEF600F00
  300. #define EMAC1_MR1 (EMAC1_BASE + 0x04)
  301. #endif
  302. #define EMAC0_MR0 (EMAC0_BASE)
  303. #define EMAC0_MR1 (EMAC0_BASE + 0x04)
  304. #define EMAC0_TMR0 (EMAC0_BASE + 0x08)
  305. #define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
  306. #define EMAC0_RXM (EMAC0_BASE + 0x10)
  307. #define EMAC0_ISR (EMAC0_BASE + 0x14)
  308. #define EMAC0_IER (EMAC0_BASE + 0x18)
  309. #define EMAC0_IAH (EMAC0_BASE + 0x1c)
  310. #define EMAC0_IAL (EMAC0_BASE + 0x20)
  311. #define EMAC0_PTR (EMAC0_BASE + 0x2c)
  312. #define EMAC0_PAUSE_TIME_REG EMAC0_PTR
  313. #define EMAC0_IPGVR (EMAC0_BASE + 0x58)
  314. #define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
  315. #define EMAC0_STACR (EMAC0_BASE + 0x5c)
  316. #define EMAC0_TRTR (EMAC0_BASE + 0x60)
  317. #define EMAC0_RWMR (EMAC0_BASE + 0x64)
  318. #define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
  319. /* bit definitions */
  320. /* MODE REG 0 */
  321. #define EMAC_MR0_RXI (0x80000000)
  322. #define EMAC_MR0_TXI (0x40000000)
  323. #define EMAC_MR0_SRST (0x20000000)
  324. #define EMAC_MR0_TXE (0x10000000)
  325. #define EMAC_MR0_RXE (0x08000000)
  326. #define EMAC_MR0_WKE (0x04000000)
  327. /* on 440GX EMAC_MR1 has a different layout! */
  328. #if defined(CONFIG_440GX) || \
  329. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  330. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  331. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  332. defined(CONFIG_405EX)
  333. /* MODE Reg 1 */
  334. #define EMAC_MR1_FDE (0x80000000)
  335. #define EMAC_MR1_ILE (0x40000000)
  336. #define EMAC_MR1_VLE (0x20000000)
  337. #define EMAC_MR1_EIFC (0x10000000)
  338. #define EMAC_MR1_APP (0x08000000)
  339. #define EMAC_MR1_RSVD (0x06000000)
  340. #define EMAC_MR1_IST (0x01000000)
  341. #define EMAC_MR1_MF_1000GPCS (0x00C00000)
  342. #define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
  343. #define EMAC_MR1_MF_100MBPS (0x00400000)
  344. #define EMAC_MR1_RFS_MASK (0x00380000)
  345. #define EMAC_MR1_RFS_16K (0x00280000)
  346. #define EMAC_MR1_RFS_8K (0x00200000)
  347. #define EMAC_MR1_RFS_4K (0x00180000)
  348. #define EMAC_MR1_RFS_2K (0x00100000)
  349. #define EMAC_MR1_RFS_1K (0x00080000)
  350. #define EMAC_MR1_TX_FIFO_MASK (0x00070000)
  351. #define EMAC_MR1_TX_FIFO_16K (0x00050000)
  352. #define EMAC_MR1_TX_FIFO_8K (0x00040000)
  353. #define EMAC_MR1_TX_FIFO_4K (0x00030000)
  354. #define EMAC_MR1_TX_FIFO_2K (0x00020000)
  355. #define EMAC_MR1_TX_FIFO_1K (0x00010000)
  356. #define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
  357. #define EMAC_MR1_MWSW (0x00007000)
  358. #define EMAC_MR1_JUMBO_ENABLE (0x00000800)
  359. #define EMAC_MR1_IPPA (0x000007c0)
  360. #define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
  361. #define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
  362. #define EMAC_MR1_OBCI_GT100 (0x00000020)
  363. #define EMAC_MR1_OBCI_100 (0x00000018)
  364. #define EMAC_MR1_OBCI_83 (0x00000010)
  365. #define EMAC_MR1_OBCI_66 (0x00000008)
  366. #define EMAC_MR1_RSVD1 (0x00000007)
  367. #else /* defined(CONFIG_440GX) */
  368. /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
  369. #define EMAC_MR1_FDE 0x80000000
  370. #define EMAC_MR1_ILE 0x40000000
  371. #define EMAC_MR1_VLE 0x20000000
  372. #define EMAC_MR1_EIFC 0x10000000
  373. #define EMAC_MR1_APP 0x08000000
  374. #define EMAC_MR1_AEMI 0x02000000
  375. #define EMAC_MR1_IST 0x01000000
  376. #define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
  377. #define EMAC_MR1_MF_100MBPS 0x00400000
  378. #define EMAC_MR1_RFS_MASK 0x00300000
  379. #define EMAC_MR1_RFS_4K 0x00300000
  380. #define EMAC_MR1_RFS_2K 0x00200000
  381. #define EMAC_MR1_RFS_1K 0x00100000
  382. #define EMAC_MR1_RFS_512 0x00000000
  383. #define EMAC_MR1_TX_FIFO_MASK 0x000c0000
  384. #define EMAC_MR1_TX_FIFO_2K 0x00080000
  385. #define EMAC_MR1_TX_FIFO_1K 0x00040000
  386. #define EMAC_MR1_TX_FIFO_512 0x00000000
  387. #define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
  388. #define EMAC_MR1_TR0_MULTI 0x00008000
  389. #define EMAC_MR1_TR1_DEPEND 0x00004000
  390. #define EMAC_MR1_TR1_MULTI 0x00002000
  391. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  392. #define EMAC_MR1_JUMBO_ENABLE 0x00001000
  393. #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
  394. #endif /* defined(CONFIG_440GX) */
  395. #define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
  396. #if defined(CONFIG_405EZ)
  397. /* 405EZ only supports 512 bytes fifos */
  398. #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
  399. #else
  400. /* Set receive fifo to 4k and tx fifo to 2k */
  401. #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
  402. #endif
  403. /* Transmit Mode Register 0 */
  404. #define EMAC_TMR0_GNP0 (0x80000000)
  405. #define EMAC_TMR0_GNP1 (0x40000000)
  406. #define EMAC_TMR0_GNPD (0x20000000)
  407. #define EMAC_TMR0_FC (0x10000000)
  408. /* Receive Mode Register */
  409. #define EMAC_RMR_SP (0x80000000)
  410. #define EMAC_RMR_SFCS (0x40000000)
  411. #define EMAC_RMR_ARRP (0x20000000)
  412. #define EMAC_RMR_ARP (0x10000000)
  413. #define EMAC_RMR_AROP (0x08000000)
  414. #define EMAC_RMR_ARPI (0x04000000)
  415. #define EMAC_RMR_PPP (0x02000000)
  416. #define EMAC_RMR_PME (0x01000000)
  417. #define EMAC_RMR_PMME (0x00800000)
  418. #define EMAC_RMR_IAE (0x00400000)
  419. #define EMAC_RMR_MIAE (0x00200000)
  420. #define EMAC_RMR_BAE (0x00100000)
  421. #define EMAC_RMR_MAE (0x00080000)
  422. /* Interrupt Status & enable Regs */
  423. #define EMAC_ISR_OVR (0x02000000)
  424. #define EMAC_ISR_PP (0x01000000)
  425. #define EMAC_ISR_BP (0x00800000)
  426. #define EMAC_ISR_RP (0x00400000)
  427. #define EMAC_ISR_SE (0x00200000)
  428. #define EMAC_ISR_SYE (0x00100000)
  429. #define EMAC_ISR_BFCS (0x00080000)
  430. #define EMAC_ISR_PTLE (0x00040000)
  431. #define EMAC_ISR_ORE (0x00020000)
  432. #define EMAC_ISR_IRE (0x00010000)
  433. #define EMAC_ISR_DBDM (0x00000200)
  434. #define EMAC_ISR_DB0 (0x00000100)
  435. #define EMAC_ISR_SE0 (0x00000080)
  436. #define EMAC_ISR_TE0 (0x00000040)
  437. #define EMAC_ISR_DB1 (0x00000020)
  438. #define EMAC_ISR_SE1 (0x00000010)
  439. #define EMAC_ISR_TE1 (0x00000008)
  440. #define EMAC_ISR_MOS (0x00000002)
  441. #define EMAC_ISR_MOF (0x00000001)
  442. /* STA CONTROL REG */
  443. #define EMAC_STACR_OC (0x00008000)
  444. #define EMAC_STACR_PHYE (0x00004000)
  445. #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
  446. #define EMAC_STACR_INDIRECT_MODE (0x00002000)
  447. #define EMAC_STACR_WRITE (0x00000800) /* $BUC */
  448. #define EMAC_STACR_READ (0x00001000) /* $BUC */
  449. #define EMAC_STACR_OP_MASK (0x00001800)
  450. #define EMAC_STACR_MDIO_ADDR (0x00000000)
  451. #define EMAC_STACR_MDIO_WRITE (0x00000800)
  452. #define EMAC_STACR_MDIO_READ (0x00001800)
  453. #define EMAC_STACR_MDIO_READ_INC (0x00001000)
  454. #else
  455. #define EMAC_STACR_WRITE (0x00002000)
  456. #define EMAC_STACR_READ (0x00001000)
  457. #endif
  458. #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
  459. #define EMAC_STACR_CLK_66MHZ (0x00000400)
  460. #define EMAC_STACR_CLK_100MHZ (0x00000C00)
  461. /* Transmit Request Threshold Register */
  462. #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
  463. #define EMAC_TRTR_192 (0x10000000)
  464. #define EMAC_TRTR_128 (0x01000000)
  465. /* the follwing defines are for the MadMAL status and control registers. */
  466. /* For bits 0..5 look at the mal.h file */
  467. #define EMAC_TX_CTRL_GFCS (0x0200)
  468. #define EMAC_TX_CTRL_GP (0x0100)
  469. #define EMAC_TX_CTRL_ISA (0x0080)
  470. #define EMAC_TX_CTRL_RSA (0x0040)
  471. #define EMAC_TX_CTRL_IVT (0x0020)
  472. #define EMAC_TX_CTRL_RVT (0x0010)
  473. #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
  474. #define EMAC_TX_ST_BFCS (0x0200)
  475. #define EMAC_TX_ST_BPP (0x0100)
  476. #define EMAC_TX_ST_LCS (0x0080)
  477. #define EMAC_TX_ST_ED (0x0040)
  478. #define EMAC_TX_ST_EC (0x0020)
  479. #define EMAC_TX_ST_LC (0x0010)
  480. #define EMAC_TX_ST_MC (0x0008)
  481. #define EMAC_TX_ST_SC (0x0004)
  482. #define EMAC_TX_ST_UR (0x0002)
  483. #define EMAC_TX_ST_SQE (0x0001)
  484. #define EMAC_TX_ST_DEFAULT (0x03F3)
  485. /* madmal receive status / Control bits */
  486. #define EMAC_RX_ST_OE (0x0200)
  487. #define EMAC_RX_ST_PP (0x0100)
  488. #define EMAC_RX_ST_BP (0x0080)
  489. #define EMAC_RX_ST_RP (0x0040)
  490. #define EMAC_RX_ST_SE (0x0020)
  491. #define EMAC_RX_ST_AE (0x0010)
  492. #define EMAC_RX_ST_BFCS (0x0008)
  493. #define EMAC_RX_ST_PTL (0x0004)
  494. #define EMAC_RX_ST_ORE (0x0002)
  495. #define EMAC_RX_ST_IRE (0x0001)
  496. /* all the errors we care about */
  497. #define EMAC_RX_ERRORS (0x03FF)
  498. #endif /* _PPC4XX_ENET_H_ */