ppc405.h 34 KB

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  1. /*----------------------------------------------------------------------------+
  2. | This source code is dual-licensed. You may use it under the terms of the
  3. | GNU General Public License version 2, or under the license below.
  4. |
  5. | This source code has been made available to you by IBM on an AS-IS
  6. | basis. Anyone receiving this source is licensed under IBM
  7. | copyrights to use it in any way he or she deems fit, including
  8. | copying it, modifying it, compiling it, and redistributing it either
  9. | with or without modifications. No license under IBM patents or
  10. | patent applications is to be implied by the copyright license.
  11. |
  12. | Any user of this software should understand that IBM cannot provide
  13. | technical support for this software and will not be responsible for
  14. | any consequences resulting from the use of this software.
  15. |
  16. | Any person who transfers this source code or any derivative work
  17. | must include the IBM copyright notice, this paragraph, and the
  18. | preceding two paragraphs in the transferred software.
  19. |
  20. | COPYRIGHT I B M CORPORATION 1999
  21. | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  22. +----------------------------------------------------------------------------*/
  23. #ifndef __PPC405_H__
  24. #define __PPC405_H__
  25. /* Define bits and masks for real-mode storage attribute control registers */
  26. #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
  27. #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
  28. #ifndef CONFIG_IOP480
  29. #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
  30. #else
  31. #define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
  32. #endif
  33. /******************************************************************************
  34. * Special for PPC405GP
  35. ******************************************************************************/
  36. /******************************************************************************
  37. * DMA
  38. ******************************************************************************/
  39. #define DMA_DCR_BASE 0x100
  40. #define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
  41. #define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
  42. #define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
  43. #define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
  44. #define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
  45. #define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
  46. #define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
  47. #define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
  48. #define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
  49. #define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
  50. #define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
  51. #define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
  52. #define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
  53. #define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
  54. #define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
  55. #define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
  56. #define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
  57. #define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
  58. #define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
  59. #define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
  60. #define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */
  61. #define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
  62. #define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */
  63. #ifndef CONFIG_405EP
  64. /******************************************************************************
  65. * Decompression Controller
  66. ******************************************************************************/
  67. #define DECOMP_DCR_BASE 0x14
  68. #define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
  69. #define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
  70. /* values for kiar register - indirect addressing of these regs */
  71. #define KCONF 0x40 /* decompression core config register */
  72. #endif
  73. /******************************************************************************
  74. * Power Management
  75. ******************************************************************************/
  76. #ifdef CONFIG_405EX
  77. #define POWERMAN_DCR_BASE 0xb0
  78. #else
  79. #define POWERMAN_DCR_BASE 0xb8
  80. #endif
  81. #define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */
  82. #define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */
  83. #define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */
  84. /******************************************************************************
  85. * Extrnal Bus Controller
  86. ******************************************************************************/
  87. /* values for EBC0_CFGADDR register - indirect addressing of these regs */
  88. #define PB0CR 0x00 /* periph bank 0 config reg */
  89. #define PB1CR 0x01 /* periph bank 1 config reg */
  90. #define PB2CR 0x02 /* periph bank 2 config reg */
  91. #define PB3CR 0x03 /* periph bank 3 config reg */
  92. #define PB4CR 0x04 /* periph bank 4 config reg */
  93. #ifndef CONFIG_405EP
  94. #define PB5CR 0x05 /* periph bank 5 config reg */
  95. #define PB6CR 0x06 /* periph bank 6 config reg */
  96. #define PB7CR 0x07 /* periph bank 7 config reg */
  97. #endif
  98. #define PB0AP 0x10 /* periph bank 0 access parameters */
  99. #define PB1AP 0x11 /* periph bank 1 access parameters */
  100. #define PB2AP 0x12 /* periph bank 2 access parameters */
  101. #define PB3AP 0x13 /* periph bank 3 access parameters */
  102. #define PB4AP 0x14 /* periph bank 4 access parameters */
  103. #ifndef CONFIG_405EP
  104. #define PB5AP 0x15 /* periph bank 5 access parameters */
  105. #define PB6AP 0x16 /* periph bank 6 access parameters */
  106. #define PB7AP 0x17 /* periph bank 7 access parameters */
  107. #endif
  108. #define PBEAR 0x20 /* periph bus error addr reg */
  109. #define PBESR0 0x21 /* periph bus error status reg 0 */
  110. #define PBESR1 0x22 /* periph bus error status reg 1 */
  111. #define EBC0_CFG 0x23 /* external bus configuration reg */
  112. #ifdef CONFIG_405EP
  113. /******************************************************************************
  114. * Control
  115. ******************************************************************************/
  116. #define CNTRL_DCR_BASE 0x0f0
  117. #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
  118. #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */
  119. #define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
  120. #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
  121. #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */
  122. #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */
  123. #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
  124. #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
  125. #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
  126. #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
  127. #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
  128. #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
  129. #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
  130. #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
  131. #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
  132. #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
  133. /* Bit definitions */
  134. #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
  135. #define PLLMR0_CPU_DIV_BYPASS 0x00000000
  136. #define PLLMR0_CPU_DIV_2 0x00100000
  137. #define PLLMR0_CPU_DIV_3 0x00200000
  138. #define PLLMR0_CPU_DIV_4 0x00300000
  139. #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
  140. #define PLLMR0_CPU_PLB_DIV_1 0x00000000
  141. #define PLLMR0_CPU_PLB_DIV_2 0x00010000
  142. #define PLLMR0_CPU_PLB_DIV_3 0x00020000
  143. #define PLLMR0_CPU_PLB_DIV_4 0x00030000
  144. #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
  145. #define PLLMR0_OPB_PLB_DIV_1 0x00000000
  146. #define PLLMR0_OPB_PLB_DIV_2 0x00001000
  147. #define PLLMR0_OPB_PLB_DIV_3 0x00002000
  148. #define PLLMR0_OPB_PLB_DIV_4 0x00003000
  149. #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
  150. #define PLLMR0_EXB_PLB_DIV_2 0x00000000
  151. #define PLLMR0_EXB_PLB_DIV_3 0x00000100
  152. #define PLLMR0_EXB_PLB_DIV_4 0x00000200
  153. #define PLLMR0_EXB_PLB_DIV_5 0x00000300
  154. #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
  155. #define PLLMR0_MAL_PLB_DIV_1 0x00000000
  156. #define PLLMR0_MAL_PLB_DIV_2 0x00000010
  157. #define PLLMR0_MAL_PLB_DIV_3 0x00000020
  158. #define PLLMR0_MAL_PLB_DIV_4 0x00000030
  159. #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
  160. #define PLLMR0_PCI_PLB_DIV_1 0x00000000
  161. #define PLLMR0_PCI_PLB_DIV_2 0x00000001
  162. #define PLLMR0_PCI_PLB_DIV_3 0x00000002
  163. #define PLLMR0_PCI_PLB_DIV_4 0x00000003
  164. #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
  165. #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
  166. #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
  167. #define PLLMR1_FBMUL_DIV_16 0x00000000
  168. #define PLLMR1_FBMUL_DIV_1 0x00100000
  169. #define PLLMR1_FBMUL_DIV_2 0x00200000
  170. #define PLLMR1_FBMUL_DIV_3 0x00300000
  171. #define PLLMR1_FBMUL_DIV_4 0x00400000
  172. #define PLLMR1_FBMUL_DIV_5 0x00500000
  173. #define PLLMR1_FBMUL_DIV_6 0x00600000
  174. #define PLLMR1_FBMUL_DIV_7 0x00700000
  175. #define PLLMR1_FBMUL_DIV_8 0x00800000
  176. #define PLLMR1_FBMUL_DIV_9 0x00900000
  177. #define PLLMR1_FBMUL_DIV_10 0x00A00000
  178. #define PLLMR1_FBMUL_DIV_11 0x00B00000
  179. #define PLLMR1_FBMUL_DIV_12 0x00C00000
  180. #define PLLMR1_FBMUL_DIV_13 0x00D00000
  181. #define PLLMR1_FBMUL_DIV_14 0x00E00000
  182. #define PLLMR1_FBMUL_DIV_15 0x00F00000
  183. #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
  184. #define PLLMR1_FWDVA_DIV_8 0x00000000
  185. #define PLLMR1_FWDVA_DIV_7 0x00010000
  186. #define PLLMR1_FWDVA_DIV_6 0x00020000
  187. #define PLLMR1_FWDVA_DIV_5 0x00030000
  188. #define PLLMR1_FWDVA_DIV_4 0x00040000
  189. #define PLLMR1_FWDVA_DIV_3 0x00050000
  190. #define PLLMR1_FWDVA_DIV_2 0x00060000
  191. #define PLLMR1_FWDVA_DIV_1 0x00070000
  192. #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
  193. #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
  194. /* Defines for CPC0_EPRCSR register */
  195. #define CPC0_EPRCSR_E0NFE 0x80000000
  196. #define CPC0_EPRCSR_E1NFE 0x40000000
  197. #define CPC0_EPRCSR_E1RPP 0x00000080
  198. #define CPC0_EPRCSR_E0RPP 0x00000040
  199. #define CPC0_EPRCSR_E1ERP 0x00000020
  200. #define CPC0_EPRCSR_E0ERP 0x00000010
  201. #define CPC0_EPRCSR_E1PCI 0x00000002
  202. #define CPC0_EPRCSR_E0PCI 0x00000001
  203. /* Defines for CPC0_PCI Register */
  204. #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
  205. #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
  206. #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */
  207. /* Defines for CPC0_BOOR Register */
  208. #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
  209. /* Defines for CPC0_PLLMR1 Register fields */
  210. #define PLL_ACTIVE 0x80000000
  211. #define CPC0_PLLMR1_SSCS 0x80000000
  212. #define PLL_RESET 0x40000000
  213. #define CPC0_PLLMR1_PLLR 0x40000000
  214. /* Feedback multiplier */
  215. #define PLL_FBKDIV 0x00F00000
  216. #define CPC0_PLLMR1_FBDV 0x00F00000
  217. #define PLL_FBKDIV_16 0x00000000
  218. #define PLL_FBKDIV_1 0x00100000
  219. #define PLL_FBKDIV_2 0x00200000
  220. #define PLL_FBKDIV_3 0x00300000
  221. #define PLL_FBKDIV_4 0x00400000
  222. #define PLL_FBKDIV_5 0x00500000
  223. #define PLL_FBKDIV_6 0x00600000
  224. #define PLL_FBKDIV_7 0x00700000
  225. #define PLL_FBKDIV_8 0x00800000
  226. #define PLL_FBKDIV_9 0x00900000
  227. #define PLL_FBKDIV_10 0x00A00000
  228. #define PLL_FBKDIV_11 0x00B00000
  229. #define PLL_FBKDIV_12 0x00C00000
  230. #define PLL_FBKDIV_13 0x00D00000
  231. #define PLL_FBKDIV_14 0x00E00000
  232. #define PLL_FBKDIV_15 0x00F00000
  233. /* Forward A divisor */
  234. #define PLL_FWDDIVA 0x00070000
  235. #define CPC0_PLLMR1_FWDVA 0x00070000
  236. #define PLL_FWDDIVA_8 0x00000000
  237. #define PLL_FWDDIVA_7 0x00010000
  238. #define PLL_FWDDIVA_6 0x00020000
  239. #define PLL_FWDDIVA_5 0x00030000
  240. #define PLL_FWDDIVA_4 0x00040000
  241. #define PLL_FWDDIVA_3 0x00050000
  242. #define PLL_FWDDIVA_2 0x00060000
  243. #define PLL_FWDDIVA_1 0x00070000
  244. /* Forward B divisor */
  245. #define PLL_FWDDIVB 0x00007000
  246. #define CPC0_PLLMR1_FWDVB 0x00007000
  247. #define PLL_FWDDIVB_8 0x00000000
  248. #define PLL_FWDDIVB_7 0x00001000
  249. #define PLL_FWDDIVB_6 0x00002000
  250. #define PLL_FWDDIVB_5 0x00003000
  251. #define PLL_FWDDIVB_4 0x00004000
  252. #define PLL_FWDDIVB_3 0x00005000
  253. #define PLL_FWDDIVB_2 0x00006000
  254. #define PLL_FWDDIVB_1 0x00007000
  255. /* PLL tune bits */
  256. #define PLL_TUNE_MASK 0x000003FF
  257. #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
  258. #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
  259. #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
  260. #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
  261. #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
  262. #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
  263. #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
  264. /* Defines for CPC0_PLLMR0 Register fields */
  265. /* CPU divisor */
  266. #define PLL_CPUDIV 0x00300000
  267. #define CPC0_PLLMR0_CCDV 0x00300000
  268. #define PLL_CPUDIV_1 0x00000000
  269. #define PLL_CPUDIV_2 0x00100000
  270. #define PLL_CPUDIV_3 0x00200000
  271. #define PLL_CPUDIV_4 0x00300000
  272. /* PLB divisor */
  273. #define PLL_PLBDIV 0x00030000
  274. #define CPC0_PLLMR0_CBDV 0x00030000
  275. #define PLL_PLBDIV_1 0x00000000
  276. #define PLL_PLBDIV_2 0x00010000
  277. #define PLL_PLBDIV_3 0x00020000
  278. #define PLL_PLBDIV_4 0x00030000
  279. /* OPB divisor */
  280. #define PLL_OPBDIV 0x00003000
  281. #define CPC0_PLLMR0_OPDV 0x00003000
  282. #define PLL_OPBDIV_1 0x00000000
  283. #define PLL_OPBDIV_2 0x00001000
  284. #define PLL_OPBDIV_3 0x00002000
  285. #define PLL_OPBDIV_4 0x00003000
  286. /* EBC divisor */
  287. #define PLL_EXTBUSDIV 0x00000300
  288. #define CPC0_PLLMR0_EPDV 0x00000300
  289. #define PLL_EXTBUSDIV_2 0x00000000
  290. #define PLL_EXTBUSDIV_3 0x00000100
  291. #define PLL_EXTBUSDIV_4 0x00000200
  292. #define PLL_EXTBUSDIV_5 0x00000300
  293. /* MAL divisor */
  294. #define PLL_MALDIV 0x00000030
  295. #define CPC0_PLLMR0_MPDV 0x00000030
  296. #define PLL_MALDIV_1 0x00000000
  297. #define PLL_MALDIV_2 0x00000010
  298. #define PLL_MALDIV_3 0x00000020
  299. #define PLL_MALDIV_4 0x00000030
  300. /* PCI divisor */
  301. #define PLL_PCIDIV 0x00000003
  302. #define CPC0_PLLMR0_PPFD 0x00000003
  303. #define PLL_PCIDIV_1 0x00000000
  304. #define PLL_PCIDIV_2 0x00000001
  305. #define PLL_PCIDIV_3 0x00000002
  306. #define PLL_PCIDIV_4 0x00000003
  307. /*
  308. *------------------------------------------------------------------------------
  309. * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  310. * assuming a 33.3MHz input clock to the 405EP.
  311. *------------------------------------------------------------------------------
  312. */
  313. #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  314. PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  315. PLL_MALDIV_1 | PLL_PCIDIV_4)
  316. #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
  317. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  318. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  319. #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  320. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  321. PLL_MALDIV_1 | PLL_PCIDIV_4)
  322. #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
  323. PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
  324. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  325. #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  326. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  327. PLL_MALDIV_1 | PLL_PCIDIV_4)
  328. #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
  329. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  330. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  331. #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  332. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  333. PLL_MALDIV_1 | PLL_PCIDIV_4)
  334. #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
  335. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  336. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  337. #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
  338. PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  339. PLL_MALDIV_1 | PLL_PCIDIV_2)
  340. #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
  341. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  342. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  343. #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  344. PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  345. PLL_MALDIV_1 | PLL_PCIDIV_3)
  346. #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
  347. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  348. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  349. #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  350. PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
  351. PLL_MALDIV_1 | PLL_PCIDIV_1)
  352. #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
  353. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  354. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  355. /*
  356. * PLL Voltage Controlled Oscillator (VCO) definitions
  357. * Maximum and minimum values (in MHz) for correct PLL operation.
  358. */
  359. #define VCO_MIN 500
  360. #define VCO_MAX 1000
  361. #elif defined(CONFIG_405EZ)
  362. #define SDR0_NAND0 0x4000
  363. #define SDR0_ULTRA0 0x4040
  364. #define SDR0_ULTRA1 0x4050
  365. #define SDR0_ICINTSTAT 0x4510
  366. #define SDR_NAND0_NDEN 0x80000000
  367. #define SDR_NAND0_NDBTEN 0x40000000
  368. #define SDR_NAND0_NDBADR_MASK 0x30000000
  369. #define SDR_NAND0_NDBPG_MASK 0x0f000000
  370. #define SDR_NAND0_NDAREN 0x00800000
  371. #define SDR_NAND0_NDRBEN 0x00400000
  372. #define SDR_ULTRA0_NDGPIOBP 0x80000000
  373. #define SDR_ULTRA0_CSN_MASK 0x78000000
  374. #define SDR_ULTRA0_CSNSEL0 0x40000000
  375. #define SDR_ULTRA0_CSNSEL1 0x20000000
  376. #define SDR_ULTRA0_CSNSEL2 0x10000000
  377. #define SDR_ULTRA0_CSNSEL3 0x08000000
  378. #define SDR_ULTRA0_EBCRDYEN 0x04000000
  379. #define SDR_ULTRA0_SPISSINEN 0x02000000
  380. #define SDR_ULTRA0_NFSRSTEN 0x01000000
  381. #define SDR_ULTRA1_LEDNENABLE 0x40000000
  382. #define SDR_ICRX_STAT 0x80000000
  383. #define SDR_ICTX0_STAT 0x40000000
  384. #define SDR_ICTX1_STAT 0x20000000
  385. #define SDR0_PINSTP 0x40
  386. /******************************************************************************
  387. * Control
  388. ******************************************************************************/
  389. /* CPR Registers */
  390. #define CPR0_CLKUP 0x020 /* CPR_CLKUPD */
  391. #define CPR0_PLLC 0x040 /* CPR_PLLC */
  392. #define CPR0_PLLD 0x060 /* CPR_PLLD */
  393. #define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */
  394. #define CPC0_PERD0 0x0e0 /* CPR_PERD0 */
  395. #define CPC0_PERD1 0x0e1 /* CPR_PERD1 */
  396. #define CPC0_PERC0 0x180 /* CPR_PERC0 */
  397. #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
  398. #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
  399. #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
  400. #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
  401. #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
  402. #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
  403. #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
  404. #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
  405. #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
  406. #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
  407. #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
  408. #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
  409. #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
  410. #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
  411. #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
  412. #else /* #ifdef CONFIG_405EP */
  413. /******************************************************************************
  414. * Control
  415. ******************************************************************************/
  416. #define CNTRL_DCR_BASE 0x0b0
  417. #define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */
  418. #define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */
  419. #define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */
  420. #define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */
  421. /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
  422. #define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */
  423. #define CPC0_ECR 0xaa /* edge conditioner register */
  424. /* Bit definitions */
  425. #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
  426. #define PLLMR_FWD_DIV_BYPASS 0xE0000000
  427. #define PLLMR_FWD_DIV_3 0xA0000000
  428. #define PLLMR_FWD_DIV_4 0x80000000
  429. #define PLLMR_FWD_DIV_6 0x40000000
  430. #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
  431. #define PLLMR_FB_DIV_1 0x02000000
  432. #define PLLMR_FB_DIV_2 0x04000000
  433. #define PLLMR_FB_DIV_3 0x06000000
  434. #define PLLMR_FB_DIV_4 0x08000000
  435. #define PLLMR_TUNING_MASK 0x01F80000
  436. #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
  437. #define PLLMR_CPU_PLB_DIV_1 0x00000000
  438. #define PLLMR_CPU_PLB_DIV_2 0x00020000
  439. #define PLLMR_CPU_PLB_DIV_3 0x00040000
  440. #define PLLMR_CPU_PLB_DIV_4 0x00060000
  441. #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
  442. #define PLLMR_OPB_PLB_DIV_1 0x00000000
  443. #define PLLMR_OPB_PLB_DIV_2 0x00008000
  444. #define PLLMR_OPB_PLB_DIV_3 0x00010000
  445. #define PLLMR_OPB_PLB_DIV_4 0x00018000
  446. #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
  447. #define PLLMR_PCI_PLB_DIV_1 0x00000000
  448. #define PLLMR_PCI_PLB_DIV_2 0x00002000
  449. #define PLLMR_PCI_PLB_DIV_3 0x00004000
  450. #define PLLMR_PCI_PLB_DIV_4 0x00006000
  451. #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
  452. #define PLLMR_EXB_PLB_DIV_2 0x00000000
  453. #define PLLMR_EXB_PLB_DIV_3 0x00000800
  454. #define PLLMR_EXB_PLB_DIV_4 0x00001000
  455. #define PLLMR_EXB_PLB_DIV_5 0x00001800
  456. /* definitions for PPC405GPr (new mode strapping) */
  457. #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
  458. #define PSR_PLL_FWD_MASK 0xC0000000
  459. #define PSR_PLL_FDBACK_MASK 0x30000000
  460. #define PSR_PLL_TUNING_MASK 0x0E000000
  461. #define PSR_PLB_CPU_MASK 0x01800000
  462. #define PSR_OPB_PLB_MASK 0x00600000
  463. #define PSR_PCI_PLB_MASK 0x00180000
  464. #define PSR_EB_PLB_MASK 0x00060000
  465. #define PSR_ROM_WIDTH_MASK 0x00018000
  466. #define PSR_ROM_LOC 0x00004000
  467. #define PSR_PCI_ASYNC_EN 0x00001000
  468. #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
  469. #define PSR_PCI_ARBIT_EN 0x00000400
  470. #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
  471. #ifndef CONFIG_IOP480
  472. /*
  473. * PLL Voltage Controlled Oscillator (VCO) definitions
  474. * Maximum and minimum values (in MHz) for correct PLL operation.
  475. */
  476. #define VCO_MIN 400
  477. #define VCO_MAX 800
  478. #endif /* #ifndef CONFIG_IOP480 */
  479. #endif /* #ifdef CONFIG_405EP */
  480. /******************************************************************************
  481. * Memory Access Layer
  482. ******************************************************************************/
  483. #if defined(CONFIG_405EZ)
  484. #define MAL_DCR_BASE 0x380
  485. #else
  486. #define MAL_DCR_BASE 0x180
  487. #endif
  488. #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
  489. #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */
  490. #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
  491. #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
  492. #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
  493. #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */
  494. #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */
  495. #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
  496. #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
  497. #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */
  498. #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */
  499. #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */
  500. #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */
  501. #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */
  502. #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */
  503. #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */
  504. #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */
  505. #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */
  506. #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */
  507. #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */
  508. #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */
  509. #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */
  510. #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
  511. #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
  512. #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
  513. #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
  514. #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
  515. #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
  516. #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
  517. /*-----------------------------------------------------------------------------
  518. | UART Register Offsets
  519. '----------------------------------------------------------------------------*/
  520. #define DATA_REG 0x00
  521. #define DL_LSB 0x00
  522. #define DL_MSB 0x01
  523. #define INT_ENABLE 0x01
  524. #define FIFO_CONTROL 0x02
  525. #define LINE_CONTROL 0x03
  526. #define MODEM_CONTROL 0x04
  527. #define LINE_STATUS 0x05
  528. #define MODEM_STATUS 0x06
  529. #define SCRATCH 0x07
  530. /******************************************************************************
  531. * On Chip Memory
  532. ******************************************************************************/
  533. #if defined(CONFIG_405EZ)
  534. #define OCM_DCR_BASE 0x020
  535. #define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */
  536. #define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */
  537. #define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */
  538. #define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */
  539. #define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */
  540. #define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */
  541. #define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */
  542. #define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */
  543. #else
  544. #define OCM_DCR_BASE 0x018
  545. #define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
  546. #define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */
  547. #define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */
  548. #endif /* CONFIG_405EZ */
  549. /******************************************************************************
  550. * GPIO macro register defines
  551. ******************************************************************************/
  552. #if defined(CONFIG_405EZ)
  553. /* Only the 405EZ has 2 GPIOs */
  554. #define GPIO_BASE 0xEF600700
  555. #define GPIO0_OR (GPIO_BASE+0x0)
  556. #define GPIO0_TCR (GPIO_BASE+0x4)
  557. #define GPIO0_OSRL (GPIO_BASE+0x8)
  558. #define GPIO0_OSRH (GPIO_BASE+0xC)
  559. #define GPIO0_TSRL (GPIO_BASE+0x10)
  560. #define GPIO0_TSRH (GPIO_BASE+0x14)
  561. #define GPIO0_ODR (GPIO_BASE+0x18)
  562. #define GPIO0_IR (GPIO_BASE+0x1C)
  563. #define GPIO0_RR1 (GPIO_BASE+0x20)
  564. #define GPIO0_RR2 (GPIO_BASE+0x24)
  565. #define GPIO0_RR3 (GPIO_BASE+0x28)
  566. #define GPIO0_ISR1L (GPIO_BASE+0x30)
  567. #define GPIO0_ISR1H (GPIO_BASE+0x34)
  568. #define GPIO0_ISR2L (GPIO_BASE+0x38)
  569. #define GPIO0_ISR2H (GPIO_BASE+0x3C)
  570. #define GPIO0_ISR3L (GPIO_BASE+0x40)
  571. #define GPIO0_ISR3H (GPIO_BASE+0x44)
  572. #define GPIO1_BASE 0xEF600800
  573. #define GPIO1_OR (GPIO1_BASE+0x0)
  574. #define GPIO1_TCR (GPIO1_BASE+0x4)
  575. #define GPIO1_OSRL (GPIO1_BASE+0x8)
  576. #define GPIO1_OSRH (GPIO1_BASE+0xC)
  577. #define GPIO1_TSRL (GPIO1_BASE+0x10)
  578. #define GPIO1_TSRH (GPIO1_BASE+0x14)
  579. #define GPIO1_ODR (GPIO1_BASE+0x18)
  580. #define GPIO1_IR (GPIO1_BASE+0x1C)
  581. #define GPIO1_RR1 (GPIO1_BASE+0x20)
  582. #define GPIO1_RR2 (GPIO1_BASE+0x24)
  583. #define GPIO1_RR3 (GPIO1_BASE+0x28)
  584. #define GPIO1_ISR1L (GPIO1_BASE+0x30)
  585. #define GPIO1_ISR1H (GPIO1_BASE+0x34)
  586. #define GPIO1_ISR2L (GPIO1_BASE+0x38)
  587. #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
  588. #define GPIO1_ISR3L (GPIO1_BASE+0x40)
  589. #define GPIO1_ISR3H (GPIO1_BASE+0x44)
  590. #elif defined(CONFIG_405EX)
  591. #define GPIO_BASE 0xEF600800
  592. #define GPIO0_OR (GPIO_BASE+0x0)
  593. #define GPIO0_TCR (GPIO_BASE+0x4)
  594. #define GPIO0_OSRL (GPIO_BASE+0x8)
  595. #define GPIO0_OSRH (GPIO_BASE+0xC)
  596. #define GPIO0_TSRL (GPIO_BASE+0x10)
  597. #define GPIO0_TSRH (GPIO_BASE+0x14)
  598. #define GPIO0_ODR (GPIO_BASE+0x18)
  599. #define GPIO0_IR (GPIO_BASE+0x1C)
  600. #define GPIO0_RR1 (GPIO_BASE+0x20)
  601. #define GPIO0_RR2 (GPIO_BASE+0x24)
  602. #define GPIO0_ISR1L (GPIO_BASE+0x30)
  603. #define GPIO0_ISR1H (GPIO_BASE+0x34)
  604. #define GPIO0_ISR2L (GPIO_BASE+0x38)
  605. #define GPIO0_ISR2H (GPIO_BASE+0x3C)
  606. #define GPIO0_ISR3L (GPIO_BASE+0x40)
  607. #define GPIO0_ISR3H (GPIO_BASE+0x44)
  608. #else /* !405EZ */
  609. #define GPIO_BASE 0xEF600700
  610. #define GPIO0_OR (GPIO_BASE+0x0)
  611. #define GPIO0_TCR (GPIO_BASE+0x4)
  612. #define GPIO0_OSRH (GPIO_BASE+0x8)
  613. #define GPIO0_OSRL (GPIO_BASE+0xC)
  614. #define GPIO0_TSRH (GPIO_BASE+0x10)
  615. #define GPIO0_TSRL (GPIO_BASE+0x14)
  616. #define GPIO0_ODR (GPIO_BASE+0x18)
  617. #define GPIO0_IR (GPIO_BASE+0x1C)
  618. #define GPIO0_RR1 (GPIO_BASE+0x20)
  619. #define GPIO0_RR2 (GPIO_BASE+0x24)
  620. #define GPIO0_ISR1H (GPIO_BASE+0x30)
  621. #define GPIO0_ISR1L (GPIO_BASE+0x34)
  622. #define GPIO0_ISR2H (GPIO_BASE+0x38)
  623. #define GPIO0_ISR2L (GPIO_BASE+0x3C)
  624. #endif /* CONFIG_405EZ */
  625. #define GPIO0_BASE GPIO_BASE
  626. #if defined(CONFIG_405EX)
  627. #define SDR0_SRST 0x0200
  628. /*
  629. * Software Reset Register
  630. */
  631. #define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
  632. #define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
  633. #define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
  634. #define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
  635. #define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
  636. #define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
  637. #define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
  638. #define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
  639. #define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
  640. #define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
  641. #define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
  642. #define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
  643. #define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
  644. #define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
  645. #define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
  646. #define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
  647. #define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
  648. #define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
  649. #define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
  650. #define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
  651. #define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
  652. #define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
  653. #define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
  654. #define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
  655. #define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
  656. #define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
  657. #define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
  658. #define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
  659. #define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
  660. #define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
  661. #define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
  662. #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
  663. #define SDR0_UART0 0x0120 /* UART0 Config */
  664. #define SDR0_UART1 0x0121 /* UART1 Config */
  665. #define SDR0_MFR 0x4300 /* SDR0_MFR reg */
  666. /* Defines for CPC0_EPRCSR register */
  667. #define CPC0_EPRCSR_E0NFE 0x80000000
  668. #define CPC0_EPRCSR_E1NFE 0x40000000
  669. #define CPC0_EPRCSR_E1RPP 0x00000080
  670. #define CPC0_EPRCSR_E0RPP 0x00000040
  671. #define CPC0_EPRCSR_E1ERP 0x00000020
  672. #define CPC0_EPRCSR_E0ERP 0x00000010
  673. #define CPC0_EPRCSR_E1PCI 0x00000002
  674. #define CPC0_EPRCSR_E0PCI 0x00000001
  675. #define CPR0_CLKUPD 0x020
  676. #define CPR0_PLLC 0x040
  677. #define CPR0_PLLD 0x060
  678. #define CPR0_CPUD 0x080
  679. #define CPR0_PLBD 0x0a0
  680. #define CPR0_OPBD0 0x0c0
  681. #define CPR0_PERD 0x0e0
  682. #define SDR0_PINSTP 0x0040
  683. #define SDR0_SDCS0 0x0060
  684. #define SDR0_SDCS_SDD (0x80000000 >> 31)
  685. /* CUST0 Customer Configuration Register0 */
  686. #define SDR0_CUST0 0x4000
  687. #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
  688. #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
  689. #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
  690. #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
  691. #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
  692. #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
  693. #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
  694. #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
  695. #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */
  696. #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */
  697. #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
  698. #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
  699. #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
  700. #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
  701. #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
  702. #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
  703. #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
  704. #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
  705. #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
  706. #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
  707. #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
  708. #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
  709. #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
  710. #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
  711. #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
  712. #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */
  713. #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */
  714. #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */
  715. #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */
  716. #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */
  717. #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */
  718. #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */
  719. #define SDR0_PFC0 0x4100
  720. #define SDR0_PFC1 0x4101
  721. #define SDR0_PFC1_U1ME 0x02000000
  722. #define SDR0_PFC1_U0ME 0x00080000
  723. #define SDR0_PFC1_U0IM 0x00040000
  724. #define SDR0_PFC1_SIS 0x00020000
  725. #define SDR0_PFC1_DMAAEN 0x00010000
  726. #define SDR0_PFC1_DMADEN 0x00008000
  727. #define SDR0_PFC1_USBEN 0x00004000
  728. #define SDR0_PFC1_AHBSWAP 0x00000020
  729. #define SDR0_PFC1_USBBIGEN 0x00000010
  730. #define SDR0_PFC1_GPT_FREQ 0x0000000f
  731. #endif
  732. /* General Purpose Timer (GPT) Register Offsets */
  733. #define GPT0_TBC 0x00000000
  734. #define GPT0_IM 0x00000018
  735. #define GPT0_ISS 0x0000001C
  736. #define GPT0_ISC 0x00000020
  737. #define GPT0_IE 0x00000024
  738. #define GPT0_COMP0 0x00000080
  739. #define GPT0_COMP1 0x00000084
  740. #define GPT0_COMP2 0x00000088
  741. #define GPT0_COMP3 0x0000008C
  742. #define GPT0_COMP4 0x00000090
  743. #define GPT0_COMP5 0x00000094
  744. #define GPT0_COMP6 0x00000098
  745. #define GPT0_MASK0 0x000000C0
  746. #define GPT0_MASK1 0x000000C4
  747. #define GPT0_MASK2 0x000000C8
  748. #define GPT0_MASK3 0x000000CC
  749. #define GPT0_MASK4 0x000000D0
  750. #define GPT0_MASK5 0x000000D4
  751. #define GPT0_MASK6 0x000000D8
  752. #define GPT0_DCT0 0x00000110
  753. #define GPT0_DCIS 0x0000011C
  754. #endif /* __PPC405_H__ */