ns9750_mem.h 6.0 KB

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  1. /***********************************************************************
  2. *
  3. * Copyright (C) 2004 by FS Forth-Systeme GmbH.
  4. * All rights reserved.
  5. *
  6. * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
  7. * @Author: Markus Pietrek
  8. * @Descr: Definitions for Memory Control Module
  9. * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. *
  26. ***********************************************************************/
  27. #ifndef FS_NS9750_MEM_H
  28. #define FS_NS9750_SYS_H
  29. #define NS9750_MEM_MODULE_BASE (0xA0700000)
  30. #define get_mem_reg_addr(c) \
  31. ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
  32. /* the register addresses */
  33. #define NS9750_MEM_CTRL (0x0000)
  34. #define NS9750_MEM_STATUS (0x0004)
  35. #define NS9750_MEM_CFG (0x0008)
  36. #define NS9750_MEM_DYN_CTRL (0x0020)
  37. #define NS9750_MEM_DYN_REFRESH (0x0024)
  38. #define NS9750_MEM_DYN_READ_CFG (0x0028)
  39. #define NS9750_MEM_DYN_TRP (0x0030)
  40. #define NS9750_MEM_DYN_TRAS (0x0034)
  41. #define NS9750_MEM_DYN_TSREX (0x0038)
  42. #define NS9750_MEM_DYN_TAPR (0x003C)
  43. #define NS9750_MEM_DYN_TDAL (0x0040)
  44. #define NS9750_MEM_DYN_TWR (0x0044)
  45. #define NS9750_MEM_DYN_TRC (0x0048)
  46. #define NS9750_MEM_DYN_TRFC (0x004C)
  47. #define NS9750_MEM_DYN_TXSR (0x0050)
  48. #define NS9750_MEM_DYN_TRRD (0x0054)
  49. #define NS9750_MEM_DYN_TMRD (0x0058)
  50. #define NS9750_MEM_STAT_EXT_WAIT (0x0080)
  51. #define NS9750_MEM_DYN_CFG_BASE (0x0100)
  52. #define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104)
  53. #define NS9750_MEM_STAT_CFG_BASE (0x0200)
  54. #define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204)
  55. #define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208)
  56. #define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C)
  57. #define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210)
  58. #define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214)
  59. #define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218)
  60. /* the vectored register addresses */
  61. #define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
  62. #define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
  63. #define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
  64. #define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
  65. #define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
  66. #define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
  67. #define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
  68. #define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
  69. #define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
  70. /* register bit fields */
  71. #define NS9750_MEM_CTRL_L (0x00000004)
  72. #define NS9750_MEM_CTRL_M (0x00000002)
  73. #define NS9750_MEM_CTRL_E (0x00000001)
  74. #define NS9750_MEM_STAT_SA (0x00000004)
  75. #define NS9750_MEM_STAT_S (0x00000002)
  76. #define NS9750_MEM_STAT_B (0x00000001)
  77. #define NS9750_MEM_CFG_CLK (0x00000010)
  78. #define NS9750_MEM_CFG_N (0x00000001)
  79. #define NS9750_MEM_DYN_CTRL_NRP (0x00004000)
  80. #define NS9750_MEM_DYN_CTRL_DP (0x00002000)
  81. #define NS9750_MEM_DYN_CTRL_I_MA (0x00000180)
  82. #define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000)
  83. #define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080)
  84. #define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100)
  85. #define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180)
  86. #define NS9750_MEM_DYN_CTRL_SR (0x00000002)
  87. #define NS9750_MEM_DYN_CTRL_CE (0x00000001)
  88. #define NS9750_MEM_DYN_REFRESH_MA (0x000007FF)
  89. #define NS9750_MEM_DYN_READ_CFG_MA (0x00000003)
  90. #define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001)
  91. #define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002)
  92. #define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003)
  93. #define NS9750_MEM_DYN_TRP_MA (0x0000000F)
  94. #define NS9750_MEM_DYN_TRAS_MA (0x0000000F)
  95. #define NS9750_MEM_DYN_TSREX_MA (0x0000000F)
  96. #define NS9750_MEM_DYN_TAPR_MA (0x0000000F)
  97. #define NS9750_MEM_DYN_TDAL_MA (0x0000000F)
  98. #define NS9750_MEM_DYN_TWR_MA (0x0000000F)
  99. #define NS9750_MEM_DYN_TRC_MA (0x0000001F)
  100. #define NS9750_MEM_DYN_TRFC_MA (0x0000001F)
  101. #define NS9750_MEM_DYN_TXSR_MA (0x0000001F)
  102. #define NS9750_MEM_DYN_TRRD_MA (0x0000000F)
  103. #define NS9750_MEM_DYN_TMRD_MA (0x0000000F)
  104. #define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F)
  105. #define NS9750_MEM_DYN_CFG_P (0x00100000)
  106. #define NS9750_MEM_DYN_CFG_BDMC (0x00080000)
  107. #define NS9750_MEM_DYN_CFG_AM (0x00004000)
  108. #define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80)
  109. #define NS9750_MEM_DYN_CFG_MD (0x00000018)
  110. #define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300)
  111. #define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100)
  112. #define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200)
  113. #define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300)
  114. #define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003)
  115. #define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001)
  116. #define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002)
  117. #define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003)
  118. #define NS9750_MEM_STAT_CFG_PSMC (0x00100000)
  119. #define NS9750_MEM_STAT_CFG_BSMC (0x00080000)
  120. #define NS9750_MEM_STAT_CFG_EW (0x00000100)
  121. #define NS9750_MEM_STAT_CFG_PB (0x00000080)
  122. #define NS9750_MEM_STAT_CFG_PC (0x00000040)
  123. #define NS9750_MEM_STAT_CFG_PM (0x00000008)
  124. #define NS9750_MEM_STAT_CFG_MW_MA (0x00000003)
  125. #define NS9750_MEM_STAT_CFG_MW_8 (0x00000000)
  126. #define NS9750_MEM_STAT_CFG_MW_16 (0x00000001)
  127. #define NS9750_MEM_STAT_CFG_MW_32 (0x00000002)
  128. #define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F)
  129. #define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F)
  130. #define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F)
  131. #define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F)
  132. #define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F)
  133. #define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F)
  134. #endif /* FS_NS9750_MEM_H */