ns9750_bbus.h 4.8 KB

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  1. /***********************************************************************
  2. *
  3. * Copyright (C) 2004 by FS Forth-Systeme GmbH.
  4. * All rights reserved.
  5. *
  6. * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
  7. * @Author: Markus Pietrek
  8. * @Descr: Definitions for BBus usage
  9. * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. *
  26. *
  27. ***********************************************************************/
  28. #ifndef FS_NS9750_BBUS_H
  29. #define FS_NS9750_BBUS_H
  30. #define NS9750_BBUS_MODULE_BASE (0x90600000)
  31. #define get_bbus_reg_addr(c) \
  32. ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
  33. /* We have support for 50 GPIO pins */
  34. #define get_gpio_cfg_reg_addr(pin) \
  35. get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
  36. /* To Read/Modify/Write a pin configuration register, use it like
  37. set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
  38. They should be wrapped by cli()/sti() */
  39. #define set_gpio_cfg_reg_val(pin,cfg) \
  40. *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
  41. ~NS9750_GPIO_CFG_MASK((pin))) |\
  42. NS9750_GPIO_CFG_VAL((pin),(cfg));
  43. #define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
  44. NS9750_GPIO_CFG_MA))
  45. #define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4))
  46. #define NS9750_GPIO_CFG_MA (0x0F)
  47. #define NS9750_GPIO_CFG_INPUT (0x00)
  48. #define NS9750_GPIO_CFG_OUTPUT (0x08)
  49. #define NS9750_GPIO_CFG_FUNC_GPIO (0x03)
  50. #define NS9750_GPIO_CFG_FUNC_2 (0x02)
  51. #define NS9750_GPIO_CFG_FUNC_1 (0x01)
  52. #define NS9750_GPIO_CFG_FUNC_0 (0x00)
  53. /* the register addresses */
  54. #define NS9750_BBUS_MASTER_RESET (0x00)
  55. #define NS9750_BBUS_GPIO_CFG_BASE (0x10)
  56. #define NS9750_BBUS_GPIO_CTRL_BASE (0x30)
  57. #define NS9750_BBUS_GPIO_STAT_BASE (0x40)
  58. #define NS9750_BBUS_MONITOR (0x50)
  59. #define NS9750_BBUS_DMA_INT_STAT (0x60)
  60. #define NS9750_BBUS_DMA_INT_ENABLE (0x64)
  61. #define NS9750_BBUS_USB_CFG (0x70)
  62. #define NS9750_BBUS_ENDIAN_CFG (0x80)
  63. #define NS9750_BBUS_ARM_WAKE_UP (0x90)
  64. /* register bit fields */
  65. #define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100)
  66. #define NS9750_BBUS_MASTER_RESET_I2C (0x00000080)
  67. #define NS9750_BBUS_MASTER_RESET_1284 (0x00000040)
  68. #define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020)
  69. #define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010)
  70. #define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008)
  71. #define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004)
  72. #define NS9750_BBUS_MASTER_RESET_USB (0x00000002)
  73. #define NS9750_BBUS_MASTER_RESET_DMA (0x00000001)
  74. /* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
  75. #define NS9750_BBUS_DMA_INT_BINT16 (0x00010000)
  76. #define NS9750_BBUS_DMA_INT_BINT15 (0x00008000)
  77. #define NS9750_BBUS_DMA_INT_BINT14 (0x00004000)
  78. #define NS9750_BBUS_DMA_INT_BINT13 (0x00002000)
  79. #define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
  80. #define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
  81. #define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
  82. #define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
  83. #define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
  84. #define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
  85. #define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
  86. #define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
  87. #define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
  88. #define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
  89. #define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
  90. #define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
  91. #define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
  92. #define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
  93. #define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
  94. #define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003)
  95. #define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
  96. #define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002)
  97. #define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001)
  98. #define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000)
  99. #define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000)
  100. #define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080)
  101. #define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040)
  102. #define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020)
  103. #define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010)
  104. #define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008)
  105. #define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004)
  106. #define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002)
  107. #define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001)
  108. #endif /* FS_NS9750_BBUS_H */