ns87308.h 8.4 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef _NS87308_H_
  24. #define _NS87308_H_
  25. #include <asm/pci_io.h>
  26. /* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
  27. functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
  28. void initialise_ns87308(void);
  29. /*
  30. * The following struct represents the GPIO registers on the NS87308/NS97307
  31. */
  32. struct GPIO
  33. {
  34. unsigned char dta1; /* 0 data port 1 */
  35. unsigned char dir1; /* 1 direction port 1 */
  36. unsigned char out1; /* 2 output type port 1 */
  37. unsigned char puc1; /* 3 pull-up control port 1 */
  38. unsigned char dta2; /* 4 data port 2 */
  39. unsigned char dir2; /* 5 direction port 2 */
  40. unsigned char out2; /* 6 output type port 2 */
  41. unsigned char puc2; /* 7 pull-up control port 2 */
  42. };
  43. /*
  44. * The following represents the power management registers on the NS87308/NS97307
  45. */
  46. #define PWM_FER1 0 /* 0 function enable reg. 1 */
  47. #define PWM_FER2 1 /* 1 function enable reg. 2 */
  48. #define PWM_PMC1 2 /* 2 power mgmt. control 1 */
  49. #define PWM_PMC2 3 /* 3 power mgmt. control 2 */
  50. #define PWM_PMC3 4 /* 4 power mgmt. control 3 */
  51. #define PWM_WDTO 5 /* 5 watchdog time-out */
  52. #define PWM_WDCF 6 /* 6 watchdog config. */
  53. #define PWM_WDST 7 /* 7 watchdog status */
  54. /*PNP config registers:
  55. * these depend on the stated of BADDR1 and BADDR0 on startup
  56. * so there's three versions here with the last two digits indicating
  57. * for which configuration their valid
  58. * the 1st of the two digits indicates the state of BADDR1
  59. * the 2st of the two digits indicates the state of BADDR0
  60. */
  61. #define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
  62. #define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
  63. #define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
  64. #define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
  65. #define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
  66. #define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
  67. #if defined(CONFIG_SYS_NS87308_BADDR_0x)
  68. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
  69. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
  70. #elif defined(CONFIG_SYS_NS87308_BADDR_10)
  71. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
  72. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
  73. #elif defined(CONFIG_SYS_NS87308_BADDR_11)
  74. #define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
  75. #define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
  76. #endif
  77. /* PnP register definitions */
  78. #define SET_RD_DATA_PORT 0x00
  79. #define SERIAL_ISOLATION 0x01
  80. #define CONFIG_CONTROL 0x02
  81. #define WAKE_CSN 0x03
  82. #define RES_DATA 0x04
  83. #define STATUS 0x05
  84. #define SET_CSN 0x06
  85. #define LOGICAL_DEVICE 0x07
  86. /*vendor defined values */
  87. #define SID_REG 0x20
  88. #define SUPOERIO_CONF1 0x21
  89. #define SUPOERIO_CONF2 0x22
  90. #define PGCS_INDEX 0x23
  91. #define PGCS_DATA 0x24
  92. /* values above 30 are different for each logical device
  93. but I can't be arsed to enter them all. the ones here
  94. are pretty consistent between all logical devices
  95. feel free to correct the situation if you want.. ;)
  96. */
  97. #define ACTIVATE 0x30
  98. #define ACTIVATE_OFF 0x00
  99. #define ACTIVATE_ON 0x01
  100. #define BASE_ADDR_HIGH 0x60
  101. #define BASE_ADDR_LOW 0x61
  102. #define LUN_CONFIG_REG 0xF0
  103. #define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
  104. #define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
  105. #define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
  106. #define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
  107. /* the logical devices*/
  108. #define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
  109. #define LDEV_KBC2 0x01
  110. #define LDEV_MOUSE 0x01
  111. #define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
  112. #define LDEV_FDC 0x03 /*floppy disk controller*/
  113. #define LDEV_PARP 0x04 /*Parallel port*/
  114. #define LDEV_UART2 0x05
  115. #define LDEV_UART1 0x06
  116. #define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
  117. #define LDEV_POWRMAN 0x08 /*Power Managment*/
  118. #define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
  119. #define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
  120. #define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
  121. #define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
  122. #define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
  123. #define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
  124. #define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
  125. #define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
  126. #define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
  127. #define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
  128. /*some functions and macro's for doing configuration */
  129. static inline void read_pnp_config(unsigned char index, unsigned char *data)
  130. {
  131. pci_writeb(index,IO_INDEX);
  132. pci_readb(IO_DATA, *data);
  133. }
  134. static inline void write_pnp_config(unsigned char index, unsigned char data)
  135. {
  136. pci_writeb(index,IO_INDEX);
  137. pci_writeb(data, IO_DATA);
  138. }
  139. static inline void pnp_set_device(unsigned char dev)
  140. {
  141. write_pnp_config(LOGICAL_DEVICE, dev);
  142. }
  143. static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
  144. {
  145. pci_writeb(index, CONFIG_SYS_ISA_IO + base);
  146. eieio();
  147. pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
  148. }
  149. /*void write_pnp_config(unsigned char index, unsigned char data);
  150. void pnp_set_device(unsigned char dev);
  151. */
  152. #define PNP_SET_DEVICE_BASE(dev,base) \
  153. pnp_set_device(dev); \
  154. write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
  155. write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
  156. write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
  157. write_pnp_config(ACTIVATE, ACTIVATE_ON);
  158. #define PNP_ACTIVATE_DEVICE(dev) \
  159. pnp_set_device(dev); \
  160. write_pnp_config(ACTIVATE, ACTIVATE_ON);
  161. #define PNP_DEACTIVATE_DEVICE(dev) \
  162. pnp_set_device(dev); \
  163. write_pnp_config(ACTIVATE, ACTIVATE_OFF);
  164. static inline void write_pgcs_config(unsigned char index, unsigned char data)
  165. {
  166. write_pnp_config(PGCS_INDEX, index);
  167. write_pnp_config(PGCS_DATA, data);
  168. }
  169. /* these macrose configure the 3 CS lines
  170. on the sandpoint board these controll NVRAM
  171. CS0 is connected to NVRAMCS
  172. CS1 is connected to NVRAMAS0
  173. CS2 is connected to NVRAMAS1
  174. */
  175. #define PGCS_CS_ASSERT_ON_WRITE 0x10
  176. #define PGCS_CS_ASSERT_ON_READ 0x20
  177. #define PNP_PGCS_CSLINE_BASE(cs, base) \
  178. write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
  179. write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
  180. #define PNP_PGCS_CSLINE_CONF(cs, conf) \
  181. write_pgcs_config(((cs) << 2) + 2, (conf) );
  182. /* The following sections are for 87308 extensions to the standard compoents it emulates */
  183. /* extensions to 16550*/
  184. #define MCR_MDSL_MSK 0xe0 /*mode select mask*/
  185. #define MCR_MDSL_UART 0x00 /*uart, default*/
  186. #define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
  187. #define MCR_MDSL_SIR 0x03 /*SIR*/
  188. #define MCR_MDSL_CIR 0x06 /*Consumer IR*/
  189. #define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
  190. #define FCR_TXFTH1 0x20 /* for interrupt trigger */
  191. /*
  192. * Default NS87308 configuration
  193. */
  194. #ifndef CONFIG_SYS_NS87308_KBC1_BASE
  195. #define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
  196. #endif
  197. #ifndef CONFIG_SYS_NS87308_RTC_BASE
  198. #define CONFIG_SYS_NS87308_RTC_BASE 0x0070
  199. #endif
  200. #ifndef CONFIG_SYS_NS87308_FDC_BASE
  201. #define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
  202. #endif
  203. #ifndef CONFIG_SYS_NS87308_LPT_BASE
  204. #define CONFIG_SYS_NS87308_LPT_BASE 0x0278
  205. #endif
  206. #ifndef CONFIG_SYS_NS87308_UART1_BASE
  207. #define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
  208. #endif
  209. #ifndef CONFIG_SYS_NS87308_UART2_BASE
  210. #define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
  211. #endif
  212. #endif /*_NS87308_H_*/