mpc85xx.h 850 B

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  1. /*
  2. * Copyright 2004, 2007 Freescale Semiconductor.
  3. * Copyright(c) 2003 Motorola Inc.
  4. */
  5. #ifndef __MPC85xx_H__
  6. #define __MPC85xx_H__
  7. #include <asm/fsl_lbc.h>
  8. /* define for common ppc_asm.tmpl */
  9. #define EXC_OFF_SYS_RESET 0x100 /* System reset */
  10. #define _START_OFFSET 0
  11. #if defined(CONFIG_E500)
  12. #include <e500.h>
  13. #endif
  14. /*
  15. * SCCR - System Clock Control Register, 9-8
  16. */
  17. #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
  18. #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
  19. #define SCCR_DFBRG_SHIFT 0
  20. #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
  21. #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
  22. #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
  23. #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
  24. #endif /* __MPC85xx_H__ */