mpc824x.h 21 KB

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  1. /*
  2. * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
  3. * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __MPC824X_H__
  24. #define __MPC824X_H__
  25. #include <config.h>
  26. /* CPU Types */
  27. #define CPU_TYPE_601 0x01 /* PPC 601 CPU */
  28. #define CPU_TYPE_602 0x02 /* PPC 602 CPU */
  29. #define CPU_TYPE_603 0x03 /* PPC 603 CPU */
  30. #define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
  31. #define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
  32. #define CPU_TYPE_604 0x04 /* PPC 604 CPU */
  33. #define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
  34. #define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
  35. #define CPU_TYPE_750 0x08 /* PPC 750 CPU */
  36. #define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
  37. #define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */
  38. #define _CACHE_ALIGN_SIZE 32 /* cache line size */
  39. /* spr976 - DMISS data tlb miss address register
  40. * spr977 - DCMP data tlb miss compare register
  41. * spr978 - HASH1 PTEG1 address register
  42. * spr980 - HASH2 PTEG2 address register
  43. * IMISS - instruction tlb miss address register
  44. * ICMP - instruction TLB mis compare register
  45. * RPA - real page address register
  46. * HID0 - hardware implemntation register
  47. * HID2 - instruction address breakpoint register
  48. */
  49. /* Kahlua/MPC8240 defines */
  50. #define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */
  51. #define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */
  52. #define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */
  53. #define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */
  54. #define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */
  55. #define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */
  56. #define CHRP_ISA_MEM_PHYS 0xfd000000
  57. #define CHRP_ISA_MEM_BUS 0x00000000
  58. #define CHRP_ISA_MEM_SIZE 0x01000000
  59. #define CHRP_ISA_IO_PHYS 0xfe000000
  60. #define CHRP_ISA_IO_BUS 0x00000000
  61. #define CHRP_ISA_IO_SIZE 0x00800000
  62. #define CHRP_PCI_IO_PHYS 0xfe800000
  63. #define CHRP_PCI_IO_BUS 0x00800000
  64. #define CHRP_PCI_IO_SIZE 0x00400000
  65. #define CHRP_PCI_MEM_PHYS 0x80000000
  66. #define CHRP_PCI_MEM_BUS 0x80000000
  67. #define CHRP_PCI_MEM_SIZE 0x7d000000
  68. #define CHRP_PCI_MEMORY_PHYS 0x00000000
  69. #define CHRP_PCI_MEMORY_BUS 0x00000000
  70. #define CHRP_PCI_MEMORY_SIZE 0x40000000
  71. #define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
  72. #define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
  73. #define PREP_ISA_IO_PHYS 0x80000000
  74. #define PREP_ISA_IO_BUS 0x00000000
  75. #define PREP_ISA_IO_SIZE 0x00800000
  76. #define PREP_PCI_IO_PHYS 0x81000000
  77. #define PREP_PCI_IO_BUS 0x01000000
  78. #define PREP_PCI_IO_SIZE 0x3e800000
  79. #define PREP_PCI_MEM_PHYS 0xc0000000
  80. #define PREP_PCI_MEM_BUS 0x00000000
  81. #define PREP_PCI_MEM_SIZE 0x3f000000
  82. #define PREP_PCI_MEMORY_PHYS 0x00000000
  83. #define PREP_PCI_MEMORY_BUS 0x80000000
  84. #define PREP_PCI_MEMORY_SIZE 0x80000000
  85. #define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
  86. #define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
  87. #define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
  88. #define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
  89. #define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
  90. #define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */
  91. #define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */
  92. #define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */
  93. #define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
  94. #define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
  95. #define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
  96. #define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
  97. #define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
  98. #define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
  99. #define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
  100. #define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
  101. #define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/
  102. #define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */
  103. #define MEM_EN_ADR 0x800000a0 /* Memory bank enable */
  104. #define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */
  105. /*-----------------------------------------------------------------------
  106. * Exception offsets (PowerPC standard)
  107. */
  108. #define EXC_OFF_RESERVED0 0x0000 /* Reserved */
  109. #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  110. #define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */
  111. #define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */
  112. #define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */
  113. #define EXC_OFF_EXTERNAL 0x0500 /* External */
  114. #define EXC_OFF_ALIGN 0x0600 /* Alignment */
  115. #define EXC_OFF_PROGRAM 0x0700 /* Program */
  116. #define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */
  117. #define EXC_OFF_DECR 0x0900 /* Decrementer */
  118. #define EXC_OFF_RESERVED1 0x0A00 /* Reserved */
  119. #define EXC_OFF_RESERVED2 0x0B00 /* Reserved */
  120. #define EXC_OFF_SYS_CALL 0x0C00 /* System Call */
  121. #define EXC_OFF_TRACE 0x0D00 /* Trace */
  122. #define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */
  123. /* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
  124. /* these found in DINK code - may not apply to 8240*/
  125. #define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */
  126. #define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */
  127. /* 0x1000 - 0x2FFF are implementation specific */
  128. /* these found in DINK code - may not apply to 8240 */
  129. #define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */
  130. #define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */
  131. #define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */
  132. #define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */
  133. #define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */
  134. #define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/
  135. #define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */
  136. #define _START_OFFSET EXC_OFF_SYS_RESET
  137. #define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */
  138. #define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */
  139. #define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */
  140. #define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */
  141. #define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */
  142. #define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */
  143. #define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */
  144. #define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */
  145. #if defined(CONFIG_SYS_ADDR_MAP_A)
  146. #define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
  147. #define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
  148. #define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
  149. #define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
  150. #else /* Assume Map B, default */
  151. #define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
  152. #define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
  153. #define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
  154. #define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
  155. #endif
  156. #define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
  157. #define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
  158. /* Macros to write to config registers. addr should be a constant in all cases */
  159. #define CONFIG_WRITE_BYTE( addr, data ) \
  160. __asm__ __volatile__( \
  161. " stwbrx %1, 0, %0\n \
  162. sync\n \
  163. stb %3, %4(%2)\n \
  164. sync " \
  165. : /* no output */ \
  166. : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
  167. "b" (CONFIG_DATA), "r" (data), \
  168. "n" ((addr) & 3));
  169. #define CONFIG_WRITE_HALFWORD( addr, data ) \
  170. __asm__ __volatile__( \
  171. " stwbrx %1, 0, %0\n \
  172. sync\n \
  173. sthbrx %3, %4, %2\n \
  174. sync " \
  175. : /* no output */ \
  176. : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
  177. "r" (CONFIG_DATA), "r" (data), \
  178. "b" ((addr) & 3));
  179. /* this assumes it's writeing on word boundaries*/
  180. #define CONFIG_WRITE_WORD( addr, data ) \
  181. __asm__ __volatile__( \
  182. " stwbrx %1, 0, %0\n \
  183. sync\n \
  184. stwbrx %3, 0, %2\n \
  185. sync " \
  186. : /* no output */ \
  187. : "r" (CONFIG_ADDR), "r" (addr), \
  188. "r" (CONFIG_DATA), "r" (data));
  189. /* Configuration register reads*/
  190. #define CONFIG_READ_BYTE( addr, reg ) \
  191. __asm__ ( \
  192. " stwbrx %1, 0, %2\n \
  193. sync\n \
  194. lbz %0, %4(%3)\n \
  195. sync " \
  196. : "=r" (reg) \
  197. : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
  198. "b" (CONFIG_DATA), "n" ((addr) & 3));
  199. #define CONFIG_READ_HALFWORD( addr, reg ) \
  200. __asm__ ( \
  201. " stwbrx %1, 0, %2\n \
  202. sync\n \
  203. lhbrx %0, %4, %3\n \
  204. sync " \
  205. : "=r" (reg) \
  206. : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
  207. "r" (CONFIG_DATA), \
  208. "b" ((addr) & 3));
  209. /* this assumes it's reading on word boundaries*/
  210. #define CONFIG_READ_WORD( addr, reg ) \
  211. __asm__ ( \
  212. " stwbrx %1, 0, %2\n \
  213. sync\n \
  214. lwbrx %0, 0, %3\n \
  215. sync " \
  216. : "=r" (reg) \
  217. : "r" (addr), "r" (CONFIG_ADDR),\
  218. "r" (CONFIG_DATA));
  219. /*
  220. * configuration register 'addresses'.
  221. * These are described in chaper 5 of the 8240 users manual.
  222. * Where the register has an abreviation in the manual, this has
  223. * been usaed here, otherwise a name in keeping with the norm has
  224. * been invented.
  225. * Note that some of these registers aren't documented in the manual.
  226. */
  227. #define PCICR 0x80000004 /* PCI Command Register */
  228. #define PCISR 0x80000006 /* PCI Status Register */
  229. #define REVID 0x80000008 /* CPU revision id */
  230. #define PIR 0x80000009 /* PCI Programming Interface Register */
  231. #define PBCCR 0x8000000b /* PCI Base Class Code Register */
  232. #define PCLSR 0x8000000c /* Processor Cache Line Size Register */
  233. #define PLTR 0x8000000d /* PCI Latancy Timer Register */
  234. #define PHTR 0x8000000e /* PCI Header Type Register */
  235. #define BISTCTRL 0x8000000f /* BIST Control */
  236. #define LMBAR 0x80000010 /* Local Base Addres Register */
  237. #define PCSRBAR 0x80000014 /* PCSR Base Address Register */
  238. #define ILR 0x8000003c /* PCI Interrupt Line Register */
  239. #define IPR 0x8000003d /* Interrupt Pin Register */
  240. #define MINGNT 0x8000003e /* MIN GNI */
  241. #define MAXLAT 0x8000003f /* MAX LAT */
  242. #define PCIACR 0x80000046 /* PCI Arbiter Control Register */
  243. #define PMCR1 0x80000070 /* Power management config. 1 */
  244. #define PMCR2 0x80000072 /* Power management config. 2 */
  245. #define ODCR 0x80000073 /* Output Driver Control Register */
  246. #define CLKDCR 0x80000074 /* CLK Driver Control Register */
  247. #if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
  248. #define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
  249. #define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
  250. #endif
  251. #define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */
  252. #define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */
  253. #define EUMBSIZE 0x00100000 /* Size of EUMB region */
  254. #define MSAR1 0x80000080 /* Memory Starting Address Register 1 */
  255. #define MSAR2 0x80000084 /* Memory Starting Address Register 2 */
  256. #define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/
  257. #define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/
  258. #define MEAR1 0x80000090 /* Memory Ending Address Register 1 */
  259. #define MEAR2 0x80000094 /* Memory Ending Address Register 2 */
  260. #define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */
  261. #define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */
  262. #define MBER 0x800000a0 /* Memory bank Enable Register*/
  263. #define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */
  264. #define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */
  265. #define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */
  266. #define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */
  267. #define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */
  268. #define ERRENR1 0x800000c0 /* Error Enableing Register 1 */
  269. #define ERRENR2 0x800000c4 /* Error Enableing Register 2 */
  270. #define ERRDR1 0x800000c1 /* Error Detection Register 1 */
  271. #define IPBESR 0x800000c3 /* Internal Processor Error Status Register */
  272. #define ERRDR2 0x800000c5 /* Error Detection Register 2 */
  273. #define PBESR 0x800000c7 /* PCI Bus Error Status Register */
  274. #define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */
  275. #define AMBOR 0x800000e0 /* Address Map B Options Register */
  276. #define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */
  277. #define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */
  278. #define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */
  279. #define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */
  280. #define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */
  281. /* some values for some of the above */
  282. #define PICR1_CF_APARK 0x00000008
  283. #define PICR1_LE_MODE 0x00000020
  284. #define PICR1_ST_GATH_EN 0x00000040
  285. #if defined(CONFIG_MPC8240)
  286. #define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
  287. #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
  288. #define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */
  289. #define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
  290. #define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */
  291. #define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */
  292. #define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */
  293. #define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */
  294. #define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
  295. #define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
  296. #define MIOCR1_SHIFT 2
  297. #define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
  298. #define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
  299. #define MIOCR2_SHIFT 3
  300. #define ODCR_ADR_X 0x80000070 /* Output Driver Control register */
  301. #define ODCR_SHIFT 3
  302. #define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */
  303. #define PMCR2_ADR_X 0x80000070
  304. #define PMCR2_SHIFT 3
  305. #define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */
  306. #else
  307. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  308. #endif
  309. #define PICR1_CF_DPARK 0x00000200
  310. #define PICR1_MCP_EN 0x00000800
  311. #define PICR1_FLASH_WR_EN 0x00001000
  312. #ifdef CONFIG_MPC8240
  313. #define PICR1_ADDRESS_MAP 0x00010000
  314. #define PIRC1_MSK 0xff000000
  315. #endif
  316. #define PICR1_PROC_TYPE_MSK 0x00060000
  317. #define PICR1_PROC_TYPE_603E 0x00040000
  318. #define PICR1_RCS0 0x00100000
  319. #define PICR2_CF_SNOOP_WS_MASK 0x000c0000
  320. #define PICR2_CF_SNOOP_WS_0WS 0x00000000
  321. #define PICR2_CF_SNOOP_WS_1WS 0x00040000
  322. #define PICR2_CF_SNOOP_WS_2WS 0x00080000
  323. #define PICR2_CF_SNOOP_WS_3WS 0x000c0000
  324. #define PICR2_CF_APHASE_WS_MASK 0x0000000c
  325. #define PICR2_CF_APHASE_WS_0WS 0x00000000
  326. #define PICR2_CF_APHASE_WS_1WS 0x00000004
  327. #define PICR2_CF_APHASE_WS_2WS 0x00000008
  328. #define PICR2_CF_APHASE_WS_3WS 0x0000000c
  329. #define MCCR1_ROMNAL_SHIFT 28
  330. #define MCCR1_ROMNAL_MSK 0xf0000000
  331. #define MCCR1_ROMFAL_SHIFT 23
  332. #define MCCR1_ROMFAL_MSK 0x0f800000
  333. #define MCCR1_DBUS_SIZE0 0x00400000
  334. #define MCCR1_BURST 0x00100000
  335. #define MCCR1_MEMGO 0x00080000
  336. #define MCCR1_SREN 0x00040000
  337. #if defined(CONFIG_MPC8240)
  338. #define MCCR1_RAM_TYPE 0x00020000
  339. #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
  340. #define MCCR1_SDRAM_EN 0x00020000
  341. #else
  342. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  343. #endif
  344. #define MCCR1_PCKEN 0x00010000
  345. #define MCCR1_BANK1ROW_SHIFT 2
  346. #define MCCR1_BANK2ROW_SHIFT 4
  347. #define MCCR1_BANK3ROW_SHIFT 6
  348. #define MCCR1_BANK4ROW_SHIFT 8
  349. #define MCCR1_BANK5ROW_SHIFT 10
  350. #define MCCR1_BANK6ROW_SHIFT 12
  351. #define MCCR1_BANK7ROW_SHIFT 14
  352. #define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
  353. #define MCCR2_TS_WAIT_TIMER_SHIFT 29
  354. #define MCCR2_ASRISE_MSK 0x1e000000
  355. #define MCCR2_ASRISE_SHIFT 25
  356. #define MCCR2_ASFALL_MSK 0x01e00000
  357. #define MCCR2_ASFALL_SHIFT 21
  358. #define MCCR2_INLINE_PAR_NOT_ECC 0x00100000
  359. #define MCCR2_WRITE_PARITY_CHK 0x00080000
  360. #define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000
  361. #ifdef CONFIG_MPC8240
  362. #define MCCR2_ECC_EN 0x00020000
  363. #define MCCR2_EDO 0x00010000
  364. #endif
  365. #define MCCR2_REFINT_MSK 0x0000fffc
  366. #define MCCR2_REFINT_SHIFT 2
  367. #define MCCR2_RSV_PG 0x00000002
  368. #define MCCR2_PMW_PAR 0x00000001
  369. #define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/
  370. #define MCCR3_BSTOPRE2TO5_SHIFT 28
  371. #define MCCR3_REFREC_MSK 0x0f000000
  372. #define MCCR3_REFREC_SHIFT 24
  373. #ifdef CONFIG_MPC8240
  374. #define MCCR3_RDLAT_MSK 0x00f00000
  375. #define MCCR3_RDLAT_SHIFT 20
  376. #define MCCR3_CPX 0x00010000
  377. #define MCCR3_RAS6P_MSK 0x00078000
  378. #define MCCR3_RAS6P_SHIFT 15
  379. #define MCCR3_CAS5_MSK 0x00007000
  380. #define MCCR3_CAS5_SHIFT 12
  381. #define MCCR3_CP4_MSK 0x00000e00
  382. #define MCCR3_CP4_SHIFT 9
  383. #define MCCR3_CAS3_MSK 0x000001c0
  384. #define MCCR3_CAS3_SHIFT 6
  385. #define MCCR3_RCD2_MSK 0x00000038
  386. #define MCCR3_RCD2_SHIFT 3
  387. #define MCCR3_RP1_MSK 0x00000007
  388. #define MCCR3_RP1_SHIFT 0
  389. #endif
  390. #define MCCR4_PRETOACT_MSK 0xf0000000
  391. #define MCCR4_PRETOACT_SHIFT 28
  392. #define MCCR4_ACTTOPRE_MSK 0x0f000000
  393. #define MCCR4_ACTTOPRE_SHIFT 24
  394. #define MCCR4_WMODE 0x00800000
  395. #define MCCR4_INLINE 0x00400000
  396. #if defined(CONFIG_MPC8240)
  397. #define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/
  398. #elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
  399. #define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */
  400. #else
  401. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  402. #endif
  403. #define MCCR4_REGISTERED 0x00100000
  404. #define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/
  405. #define MCCR4_BSTOPRE0TO1_SHIFT 18
  406. #define MCCR4_REGDIMM 0x00008000
  407. #define MCCR4_SDMODE_MSK 0x00007f00
  408. #define MCCR4_SDMODE_SHIFT 8
  409. #define MCCR4_ACTTORW_MSK 0x000000f0
  410. #define MCCR4_ACTTORW_SHIFT 4
  411. #define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/
  412. #define MCCR4_BSTOPRE6TO9_SHIFT 0
  413. #define MCCR4_DBUS_SIZE2_SHIFT 17
  414. #define MICR_ADDR_MASK 0x0ff00000
  415. #define MICR_ADDR_SHIFT 20
  416. #define MICR_EADDR_MASK 0x30000000
  417. #define MICR_EADDR_SHIFT 28
  418. /*eumb and epic config*/
  419. #define EPIC_FPR 0x00041000
  420. #define EPIC_GCR 0x00041020
  421. #define EPIC_EICR 0x00041030
  422. #define EPIC_EVI 0x00041080
  423. #define EPIC_PI 0x00041090
  424. #define EPIC_SVR 0x000410E0
  425. #define EPIC_TFRR 0x000410F0
  426. /*
  427. * Note the information for these is rather mangled in the 8240 manual.
  428. * These are guesses.
  429. */
  430. #define EPIC_GTCCR0 0x00041100
  431. #define EPIC_GTCCR1 0x00041140
  432. #define EPIC_GTCCR2 0x00041180
  433. #define EPIC_GTCCR3 0x000411C0
  434. #define EPIC_GTBCR0 0x00041110
  435. #define EPIC_GTBCR1 0x00041150
  436. #define EPIC_GTBCR2 0x00041190
  437. #define EPIC_GTBCR3 0x000411D0
  438. #define EPIC_GTVPR0 0x00041120
  439. #define EPIC_GTVPR1 0x00041160
  440. #define EPIC_GTVPR2 0x000411a0
  441. #define EPIC_GTVPR3 0x000411e0
  442. #define EPIC_GTDR0 0x00041130
  443. #define EPIC_GTDR1 0x00041170
  444. #define EPIC_GTDR2 0x000411b0
  445. #define EPIC_GTDR3 0x000411f0
  446. #define EPIC_IVPR0 0x00050200
  447. #define EPIC_IVPR1 0x00050220
  448. #define EPIC_IVPR2 0x00050240
  449. #define EPIC_IVPR3 0x00050260
  450. #define EPIC_IVPR4 0x00050280
  451. #define EPIC_SVPR0 0x00050200
  452. #define EPIC_SVPR1 0x00050220
  453. #define EPIC_SVPR2 0x00050240
  454. #define EPIC_SVPR3 0x00050260
  455. #define EPIC_SVPR4 0x00050280
  456. #define EPIC_SVPR5 0x000502A0
  457. #define EPIC_SVPR6 0x000502C0
  458. #define EPIC_SVPR7 0x000502E0
  459. #define EPIC_SVPR8 0x00050300
  460. #define EPIC_SVPR9 0x00050320
  461. #define EPIC_SVPRa 0x00050340
  462. #define EPIC_SVPRb 0x00050360
  463. #define EPIC_SVPRc 0x00050380
  464. #define EPIC_SVPRd 0x000503A0
  465. #define EPIC_SVPRe 0x000503C0
  466. #define EPIC_SVPRf 0x000503E0
  467. /* MPC8240 Byte Swap/PCI Support Macros */
  468. #define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
  469. #define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
  470. (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
  471. #define PCISWAP(x) LONGSWAP(x)
  472. #ifndef __ASSEMBLY__
  473. /*
  474. * MPC107 Support
  475. *
  476. */
  477. unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
  478. void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
  479. void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
  480. void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
  481. void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
  482. unsigned char mpc824x_mpc107_read8(unsigned int address);
  483. unsigned short mpc824x_mpc107_read16(unsigned int address);
  484. unsigned int mpc824x_mpc107_read32(unsigned int address);
  485. unsigned int mpc824x_eummbar_read(unsigned int regNum);
  486. void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
  487. #ifdef CONFIG_PCI
  488. struct pci_controller;
  489. void pci_cpm824x_init(struct pci_controller* hose);
  490. #endif
  491. #endif /* __ASSEMBLY__ */
  492. #endif /* __MPC824X_H__ */