mpc8220.h 29 KB

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  1. /*
  2. * include/mpc8220.h
  3. *
  4. * Prototypes, etc. for the Motorola MPC8220
  5. * embedded cpu chips
  6. *
  7. * 2004 (c) Freescale, Inc.
  8. * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #ifndef __MPC8220_H__
  29. #define __MPC8220_H__
  30. /* Processor name */
  31. #if defined(CONFIG_MPC8220)
  32. #define CPU_ID_STR "MPC8220"
  33. #endif
  34. /* Exception offsets (PowerPC standard) */
  35. #define EXC_OFF_SYS_RESET 0x0100
  36. #define _START_OFFSET EXC_OFF_SYS_RESET
  37. /* Internal memory map */
  38. /* MPC8220 Internal Register MMAP */
  39. #define MMAP_MBAR (CONFIG_SYS_MBAR + 0x00000000) /* chip selects */
  40. #define MMAP_MEMCTL (CONFIG_SYS_MBAR + 0x00000100) /* sdram controller */
  41. #define MMAP_XLBARB (CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control */
  42. #define MMAP_CDM (CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */
  43. #define MMAP_VDOPLL (CONFIG_SYS_MBAR + 0x00000400) /* video PLL */
  44. #define MMAP_FB (CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller */
  45. #define MMAP_PCFG (CONFIG_SYS_MBAR + 0x00000600) /* port config */
  46. #define MMAP_ICTL (CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller */
  47. #define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers */
  48. #define MMAP_SLTMR (CONFIG_SYS_MBAR + 0x00000900) /* slice timers */
  49. #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) /* gpio module */
  50. #define MMAP_XCPCI (CONFIG_SYS_MBAR + 0x00000B00) /* pci controller */
  51. #define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter */
  52. #define MMAP_EXTDMA1 (CONFIG_SYS_MBAR + 0x00000D00) /* external dma1 */
  53. #define MMAP_EXTDMA2 (CONFIG_SYS_MBAR + 0x00000E00) /* external dma1 */
  54. #define MMAP_USBH (CONFIG_SYS_MBAR + 0x00001000) /* usb host */
  55. #define MMAP_CMTMR (CONFIG_SYS_MBAR + 0x00007f00) /* comm timers */
  56. #define MMAP_DMA (CONFIG_SYS_MBAR + 0x00008000) /* dma */
  57. #define MMAP_USBD (CONFIG_SYS_MBAR + 0x00008200) /* usb device */
  58. #define MMAP_COMMPCI (CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs */
  59. #define MMAP_1284 (CONFIG_SYS_MBAR + 0x00008500) /* 1284 */
  60. #define MMAP_PEV (CONFIG_SYS_MBAR + 0x00008600) /* print engine video */
  61. #define MMAP_PSC1 (CONFIG_SYS_MBAR + 0x00008800) /* psc1 block */
  62. #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller */
  63. #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1 */
  64. #define MMAP_FEC2 (CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2 */
  65. #define MMAP_JBIGRAM (CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM */
  66. #define MMAP_JBIG (CONFIG_SYS_MBAR + 0x0000c000) /* jbig */
  67. #define MMAP_PDLA (CONFIG_SYS_MBAR + 0x00010000) /* */
  68. #define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config */
  69. #define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00020000) /* SRAM */
  70. #define SRAM_SIZE 0x8000 /* 32 KB */
  71. /* ------------------------------------------------------------------------ */
  72. /*
  73. * Macro for Programmable Serial Channel
  74. */
  75. /* equates for mode reg. 1 for channel A or B */
  76. #define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */
  77. #define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */
  78. #define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */
  79. #define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */
  80. #define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */
  81. #define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */
  82. #define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */
  83. #define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */
  84. #define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */
  85. #define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */
  86. #define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */
  87. #define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */
  88. #define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */
  89. /* equates for mode reg. 2 for channel A or B */
  90. #define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */
  91. #define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */
  92. #define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */
  93. #define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */
  94. #define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */
  95. #define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */
  96. #define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */
  97. #define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */
  98. /* equates for status reg. A or B */
  99. #define PSC_SR_BREAK 0x80000000 /* received break */
  100. #define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */
  101. #define PSC_SR_FRAMING 0x40000000 /* framing error */
  102. #define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
  103. #define PSC_SR_PARITY 0x20000000 /* parity error */
  104. #define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */
  105. #define PSC_SR_OVERRUN 0x10000000 /* overrun error */
  106. #define PSC_SR_TXEMT 0x08000000 /* transmitter empty */
  107. #define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/
  108. #define PSC_SR_FFULL 0x02000000 /* fifo full */
  109. #define PSC_SR_RXRDY 0x01000000 /* receiver ready */
  110. #define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */
  111. #define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */
  112. /* equates for clock select reg. */
  113. #define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */
  114. #define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */
  115. /* equates for command reg. A or B */
  116. #define PSC_CR_NO_COMMAND 0x00000000 /* no command */
  117. #define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */
  118. #define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */
  119. #define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */
  120. #define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */
  121. #define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */
  122. #define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */
  123. #define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */
  124. #define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */
  125. #define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */
  126. #define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */
  127. #define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */
  128. /* equates for input port change reg. */
  129. #define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */
  130. #define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */
  131. #define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */
  132. /* equates for auxiliary control reg. (timer and counter clock selects) */
  133. #define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility
  134. baud rate gen select
  135. 0 = set 1; 1 = set 2
  136. equates are set 2 ONLY */
  137. #define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */
  138. #define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */
  139. #define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */
  140. #define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */
  141. #define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */
  142. #define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */
  143. #define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */
  144. #define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */
  145. #define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */
  146. /* equates for int. status reg. */
  147. #define PSC_ISR_IPC 0x80000000 /* input port change*/
  148. #define PSC_ISR_BREAK 0x04000000 /* delta break */
  149. #define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */
  150. #define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */
  151. #define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
  152. #define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */
  153. /* equates for int. mask reg. */
  154. #define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */
  155. #define PSC_IMR_IPC 0x80000000 /* input port change*/
  156. #define PSC_IMR_BREAK 0x04000000 /* delta break */
  157. #define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */
  158. #define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */
  159. #define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
  160. #define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */
  161. /* equates for input port reg. */
  162. #define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */
  163. #define PSC_IP_TGL 0x40000000 /* test usage */
  164. #define PSC_IP_CTS 0x01000000 /* CTS */
  165. /* equates for output port bit set reg. */
  166. #define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */
  167. /* equates for output port bit reset reg. */
  168. #define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */
  169. /* equates for rx FIFO number of data reg. */
  170. #define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */
  171. /* equates for tx FIFO number of data reg. */
  172. #define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */
  173. /* equates for rx FIFO status reg */
  174. #define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */
  175. #define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
  176. #define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
  177. #define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
  178. #define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
  179. #define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
  180. #define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */
  181. #define PSC_RFSTAT_UF 0x00200000 /* Underflow */
  182. #define PSC_RFSTAT_OF 0x00100000 /* overflow */
  183. #define PSC_RFSTAT_FR 0x00080000 /* frame ready */
  184. #define PSC_RFSTAT_FULL 0x00040000 /* full */
  185. #define PSC_RFSTAT_ALARM 0x00020000 /* alarm */
  186. #define PSC_RFSTAT_EMPTY 0x00010000 /* empty */
  187. /* equates for tx FIFO status reg */
  188. #define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */
  189. #define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
  190. #define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
  191. #define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
  192. #define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
  193. #define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
  194. #define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */
  195. #define PSC_TFSTAT_UF 0x00200000 /* Underflow */
  196. #define PSC_TFSTAT_OF 0x00100000 /* overflow */
  197. #define PSC_TFSTAT_FR 0x00080000 /* frame ready */
  198. #define PSC_TFSTAT_FULL 0x00040000 /* full */
  199. #define PSC_TFSTAT_ALARM 0x00020000 /* alarm */
  200. #define PSC_TFSTAT_EMPTY 0x00010000 /* empty */
  201. /* equates for rx FIFO control reg. */
  202. #define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
  203. #define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */
  204. #define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */
  205. /* equates for tx FIFO control reg. */
  206. #define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
  207. #define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */
  208. #define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */
  209. /* equates for rx FIFO alarm reg */
  210. #define PSC_RFALARM(x) (x&0x1ff) /* Alarm */
  211. /* equates for tx FIFO alarm reg */
  212. #define PSC_TFALARM(x) (x&0x1ff) /* Alarm */
  213. /* equates for rx FIFO read pointer */
  214. #define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */
  215. /* equates for tx FIFO read pointer */
  216. #define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */
  217. /* equates for rx FIFO write pointer */
  218. #define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */
  219. /* equates for rx FIFO write pointer */
  220. #define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */
  221. /* equates for rx FIFO last read frame pointer reg */
  222. #define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
  223. /* equates for tx FIFO last read frame pointer reg */
  224. #define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
  225. /* equates for rx FIFO last write frame pointer reg */
  226. #define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
  227. /* equates for tx FIFO last write frame pointer reg */
  228. #define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
  229. /* PCI configuration (only for PLL determination)*/
  230. #define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */
  231. #define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000
  232. #define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24
  233. #define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */
  234. /* ------------------------------------------------------------------------ */
  235. /*
  236. * Macro for General Purpose Timer
  237. */
  238. /* Enable and Mode Select */
  239. #define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */
  240. #define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
  241. #define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
  242. #define GPT_CTRL_CE 0x10 /* Counter Enable */
  243. #define GPT_CTRL_STPCNT 0x04 /* Stop continous */
  244. #define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
  245. #define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
  246. #define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */
  247. #define GPT_TMS_ICT 0x01 /* Input Capture Enable */
  248. #define GPT_TMS_OCT 0x02 /* Output Capture Enable */
  249. #define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
  250. #define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
  251. #define GPT_PWM_WIDTH(x) (x & 0xffff)
  252. /* Status */
  253. #define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */
  254. #define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */
  255. #define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */
  256. #define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */
  257. #define GPT_INT_PWMP 0x04 /* PWM end of period occurred */
  258. #define GPT_INT_COMP 0x02 /* OC reference event occurred */
  259. #define GPT_INT_CAPT 0x01 /* IC reference event occurred */
  260. /* ------------------------------------------------------------------------ */
  261. /*
  262. * Port configuration
  263. */
  264. #define CONFIG_SYS_FEC1_PORT0_CONFIG 0x00000000
  265. #define CONFIG_SYS_FEC1_PORT1_CONFIG 0x00000000
  266. #define CONFIG_SYS_1284_PORT0_CONFIG 0x00000000
  267. #define CONFIG_SYS_1284_PORT1_CONFIG 0x00000000
  268. #define CONFIG_SYS_FEC2_PORT2_CONFIG 0x00000000
  269. #define CONFIG_SYS_PEV_PORT2_CONFIG 0x00000000
  270. #define CONFIG_SYS_GP0_PORT0_CONFIG 0x00000000
  271. #define CONFIG_SYS_GP1_PORT2_CONFIG 0xaaaaaac0
  272. #define CONFIG_SYS_PSC_PORT3_CONFIG 0x00020000
  273. #define CONFIG_SYS_CS1_PORT3_CONFIG 0x00000000
  274. #define CONFIG_SYS_CS2_PORT3_CONFIG 0x10000000
  275. #define CONFIG_SYS_CS3_PORT3_CONFIG 0x40000000
  276. #define CONFIG_SYS_CS4_PORT3_CONFIG 0x00000400
  277. #define CONFIG_SYS_CS5_PORT3_CONFIG 0x00000200
  278. #define CONFIG_SYS_PCI_PORT3_CONFIG 0x01400180
  279. #define CONFIG_SYS_I2C_PORT3_CONFIG 0x00000000
  280. #define CONFIG_SYS_GP2_PORT3_CONFIG 0x000200a0
  281. /* ------------------------------------------------------------------------ */
  282. /*
  283. * DRAM configuration
  284. */
  285. /* Field definitions for the control register */
  286. #define CTL_MODE_ENABLE_SHIFT 31
  287. #define CTL_CKE_SHIFT 30
  288. #define CTL_DDR_SHIFT 29
  289. #define CTL_REFRESH_SHIFT 28
  290. #define CTL_ADDRMUX_SHIFT 24
  291. #define CTL_PRECHARGE_SHIFT 23
  292. #define CTL_DRIVE_RULE_SHIFT 22
  293. #define CTL_REFRESH_INTERVAL_SHIFT 16
  294. #define CTL_DQSOEN_SHIFT 8
  295. #define CTL_BUFFERED_SHIFT 4
  296. #define CTL_REFRESH_CMD_SHIFT 2
  297. #define CTL_PRECHARGE_CMD_SHIFT 1
  298. #define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT)
  299. #define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT)
  300. #define CTL_DDR_MODE (1<<CTL_DDR_SHIFT)
  301. #define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT)
  302. #define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT)
  303. #define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT)
  304. #define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
  305. #define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT)
  306. #define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT)
  307. #define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT)
  308. #define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT)
  309. /* Field definitions for config register 1 */
  310. #define CFG1_SRD2RWP_SHIFT 28
  311. #define CFG1_SWT2RWP_SHIFT 24
  312. #define CFG1_RLATENCY_SHIFT 20
  313. #define CFG1_ACT2WR_SHIFT 16
  314. #define CFG1_PRE2ACT_SHIFT 12
  315. #define CFG1_REF2ACT_SHIFT 8
  316. #define CFG1_WLATENCY_SHIFT 4
  317. #define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT)
  318. #define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT)
  319. #define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT)
  320. #define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT)
  321. #define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT)
  322. #define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT)
  323. #define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT)
  324. /* Field definitions for config register 2 */
  325. #define CFG2_BRD2RP_SHIFT 28
  326. #define CFG2_BWT2RWP_SHIFT 24
  327. #define CFG2_BRD2WT_SHIFT 20
  328. #define CFG2_BURSTLEN_SHIFT 16
  329. #define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT)
  330. #define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT)
  331. #define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT)
  332. #define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT)
  333. /* Field definitions for the mode/extended mode register - mode
  334. * register access
  335. */
  336. #define MODE_REG_SHIFT 30
  337. #define MODE_OPMODE_SHIFT 25
  338. #define MODE_CL_SHIFT 22
  339. #define MODE_BT_SHIFT 21
  340. #define MODE_BURSTLEN_SHIFT 18
  341. #define MODE_CMD_SHIFT 16
  342. #define MODE_MODE 0
  343. #define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT)
  344. #define MODE_CL(value) ((value)<<MODE_CL_SHIFT)
  345. #define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT)
  346. #define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT)
  347. #define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT)
  348. #define MODE_CMD (1<<MODE_CMD_SHIFT)
  349. #define MODE_BURSTLEN_8 3
  350. #define MODE_BURSTLEN_4 2
  351. #define MODE_BURSTLEN_2 1
  352. #define MODE_CL_2 2
  353. #define MODE_CL_2p5 6
  354. #define MODE_OPMODE_NORMAL 0
  355. #define MODE_OPMODE_RESETDLL 2
  356. /* Field definitions for the mode/extended mode register - extended
  357. * mode register access
  358. */
  359. #define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */
  360. #define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */
  361. #define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */
  362. #define MODE_X_OPMODE_SHIFT 21
  363. #define MODE_EXTENDED (1<<MODE_REG_SHIFT)
  364. #define MODE_X_DLL_ENABLE 0
  365. #define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT)
  366. #define MODE_X_DS_NORMAL 0
  367. #define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT)
  368. #define MODE_X_QFC_DISABLED 0
  369. #define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT)
  370. #ifndef __ASSEMBLY__
  371. /*
  372. * DMA control/status registers.
  373. */
  374. struct mpc8220_dma {
  375. u32 taskBar; /* DMA + 0x00 */
  376. u32 currentPointer; /* DMA + 0x04 */
  377. u32 endPointer; /* DMA + 0x08 */
  378. u32 variablePointer;/* DMA + 0x0c */
  379. u8 IntVect1; /* DMA + 0x10 */
  380. u8 IntVect2; /* DMA + 0x11 */
  381. u16 PtdCntrl; /* DMA + 0x12 */
  382. u32 IntPend; /* DMA + 0x14 */
  383. u32 IntMask; /* DMA + 0x18 */
  384. u16 tcr_0; /* DMA + 0x1c */
  385. u16 tcr_1; /* DMA + 0x1e */
  386. u16 tcr_2; /* DMA + 0x20 */
  387. u16 tcr_3; /* DMA + 0x22 */
  388. u16 tcr_4; /* DMA + 0x24 */
  389. u16 tcr_5; /* DMA + 0x26 */
  390. u16 tcr_6; /* DMA + 0x28 */
  391. u16 tcr_7; /* DMA + 0x2a */
  392. u16 tcr_8; /* DMA + 0x2c */
  393. u16 tcr_9; /* DMA + 0x2e */
  394. u16 tcr_a; /* DMA + 0x30 */
  395. u16 tcr_b; /* DMA + 0x32 */
  396. u16 tcr_c; /* DMA + 0x34 */
  397. u16 tcr_d; /* DMA + 0x36 */
  398. u16 tcr_e; /* DMA + 0x38 */
  399. u16 tcr_f; /* DMA + 0x3a */
  400. u8 IPR0; /* DMA + 0x3c */
  401. u8 IPR1; /* DMA + 0x3d */
  402. u8 IPR2; /* DMA + 0x3e */
  403. u8 IPR3; /* DMA + 0x3f */
  404. u8 IPR4; /* DMA + 0x40 */
  405. u8 IPR5; /* DMA + 0x41 */
  406. u8 IPR6; /* DMA + 0x42 */
  407. u8 IPR7; /* DMA + 0x43 */
  408. u8 IPR8; /* DMA + 0x44 */
  409. u8 IPR9; /* DMA + 0x45 */
  410. u8 IPR10; /* DMA + 0x46 */
  411. u8 IPR11; /* DMA + 0x47 */
  412. u8 IPR12; /* DMA + 0x48 */
  413. u8 IPR13; /* DMA + 0x49 */
  414. u8 IPR14; /* DMA + 0x4a */
  415. u8 IPR15; /* DMA + 0x4b */
  416. u8 IPR16; /* DMA + 0x4c */
  417. u8 IPR17; /* DMA + 0x4d */
  418. u8 IPR18; /* DMA + 0x4e */
  419. u8 IPR19; /* DMA + 0x4f */
  420. u8 IPR20; /* DMA + 0x50 */
  421. u8 IPR21; /* DMA + 0x51 */
  422. u8 IPR22; /* DMA + 0x52 */
  423. u8 IPR23; /* DMA + 0x53 */
  424. u8 IPR24; /* DMA + 0x54 */
  425. u8 IPR25; /* DMA + 0x55 */
  426. u8 IPR26; /* DMA + 0x56 */
  427. u8 IPR27; /* DMA + 0x57 */
  428. u8 IPR28; /* DMA + 0x58 */
  429. u8 IPR29; /* DMA + 0x59 */
  430. u8 IPR30; /* DMA + 0x5a */
  431. u8 IPR31; /* DMA + 0x5b */
  432. u32 res1; /* DMA + 0x5c */
  433. u32 res2; /* DMA + 0x60 */
  434. u32 res3; /* DMA + 0x64 */
  435. u32 MDEDebug; /* DMA + 0x68 */
  436. u32 ADSDebug; /* DMA + 0x6c */
  437. u32 Value1; /* DMA + 0x70 */
  438. u32 Value2; /* DMA + 0x74 */
  439. u32 Control; /* DMA + 0x78 */
  440. u32 Status; /* DMA + 0x7c */
  441. u32 EU00; /* DMA + 0x80 */
  442. u32 EU01; /* DMA + 0x84 */
  443. u32 EU02; /* DMA + 0x88 */
  444. u32 EU03; /* DMA + 0x8c */
  445. u32 EU04; /* DMA + 0x90 */
  446. u32 EU05; /* DMA + 0x94 */
  447. u32 EU06; /* DMA + 0x98 */
  448. u32 EU07; /* DMA + 0x9c */
  449. u32 EU10; /* DMA + 0xa0 */
  450. u32 EU11; /* DMA + 0xa4 */
  451. u32 EU12; /* DMA + 0xa8 */
  452. u32 EU13; /* DMA + 0xac */
  453. u32 EU14; /* DMA + 0xb0 */
  454. u32 EU15; /* DMA + 0xb4 */
  455. u32 EU16; /* DMA + 0xb8 */
  456. u32 EU17; /* DMA + 0xbc */
  457. u32 EU20; /* DMA + 0xc0 */
  458. u32 EU21; /* DMA + 0xc4 */
  459. u32 EU22; /* DMA + 0xc8 */
  460. u32 EU23; /* DMA + 0xcc */
  461. u32 EU24; /* DMA + 0xd0 */
  462. u32 EU25; /* DMA + 0xd4 */
  463. u32 EU26; /* DMA + 0xd8 */
  464. u32 EU27; /* DMA + 0xdc */
  465. u32 EU30; /* DMA + 0xe0 */
  466. u32 EU31; /* DMA + 0xe4 */
  467. u32 EU32; /* DMA + 0xe8 */
  468. u32 EU33; /* DMA + 0xec */
  469. u32 EU34; /* DMA + 0xf0 */
  470. u32 EU35; /* DMA + 0xf4 */
  471. u32 EU36; /* DMA + 0xf8 */
  472. u32 EU37; /* DMA + 0xfc */
  473. };
  474. /*
  475. * PCI Header Registers
  476. */
  477. typedef struct mpc8220_xcpci {
  478. u32 dev_ven_id; /* 0xb00 - device/vendor ID */
  479. u32 stat_cmd_reg; /* 0xb04 - status command register */
  480. u32 class_code_rev_id; /* 0xb08 - class code / revision ID */
  481. u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */
  482. u32 base0; /* 0xb10 - base address 0 */
  483. u32 base1; /* 0xb14 - base address 1 */
  484. u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */
  485. u32 cis; /* 0xb28 - cardBus CIS pointer */
  486. u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */
  487. u32 reserved2; /* 0xb30 - expansion ROM base address */
  488. u32 reserved3; /* 0xb00 - reserved */
  489. u32 reserved4; /* 0xb00 - reserved */
  490. u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */
  491. u32 reserved5[8];
  492. /* MPC8220 specific - not accessible in PCI header space externally */
  493. u32 glb_stat_ctl; /* 0xb60 - Global Status Control */
  494. u32 target_bar0; /* 0xb64 - Target Base Address 0 */
  495. u32 target_bar1; /* 0xb68 - Target Base Address 1 */
  496. u32 target_ctrl; /* 0xb6c - Target Control */
  497. u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */
  498. u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */
  499. u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */
  500. u32 reserved6; /* 0xb7c - reserved */
  501. u32 init_win_cfg; /* 0xb80 */
  502. u32 init_ctrl; /* 0xb84 */
  503. u32 init_stat; /* 0xb88 */
  504. u32 reserved7[27];
  505. u32 cfg_adr; /* 0xbf8 */
  506. u32 reserved8;
  507. } mpc8220_xcpci_t;
  508. /* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
  509. reg1 - 1GB */
  510. #define PCI_BASE_ADDR_REG0 0x40000000
  511. #define PCI_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
  512. #define PCI_TARGET_BASE_ADDR_REG0 (CONFIG_SYS_MBAR)
  513. #define PCI_TARGET_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
  514. #define PCI_TARGET_BASE_ADDR_EN 1<<0
  515. /* PCI Global Status/Control Register (PCIGSCR) */
  516. #define PCI_GLB_STAT_CTRL_PE_SHIFT 29
  517. #define PCI_GLB_STAT_CTRL_SE_SHIFT 28
  518. #define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24
  519. #define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7
  520. #define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16
  521. #define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7
  522. #define PCI_GLB_STAT_CTRL_PEE_SHIFT 13
  523. #define PCI_GLB_STAT_CTRL_SEE_SHIFT 12
  524. #define PCI_GLB_STAT_CTRL_PR_SHIFT 0
  525. #define PCI_GLB_STAT_CTRL_PE (1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
  526. #define PCI_GLB_STAT_CTRL_SE (1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
  527. #define PCI_GLB_STAT_CTRL_PEE (1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
  528. #define PCI_GLB_STAT_CTRL_SEE (1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
  529. #define PCI_GLB_STAT_CTRL_PR (1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
  530. /* PCI Target Control Register (PCITCR) */
  531. #define PCI_TARGET_CTRL_LD_SHIFT 24
  532. #define PCI_TARGET_CTRL_P_SHIFT 16
  533. #define PCI_TARGET_CTRL_LD (1<<PCI_TARGET_CTRL_LD_SHIFT)
  534. #define PCI_TARGET_CTRL_P (1<<PCI_TARGET_CTRL_P_SHIFT)
  535. /* PCI Initiator Window Configuration Register (PCIIWCR) */
  536. #define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT 27
  537. #define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT 25
  538. #define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK 0x3
  539. #define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT 24
  540. #define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT 19
  541. #define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT 17
  542. #define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK 0x3
  543. #define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT 16
  544. #define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT 11
  545. #define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT 9
  546. #define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK 0x3
  547. #define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT 8
  548. #define PCI_INIT_WIN_CFG_WIN_MEM_READ 0x0
  549. #define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE 0x1
  550. #define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE 0x2
  551. #define PCI_INIT_WIN_CFG_WIN0_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
  552. #define PCI_INIT_WIN_CFG_WIN0_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
  553. #define PCI_INIT_WIN_CFG_WIN1_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
  554. #define PCI_INIT_WIN_CFG_WIN1_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
  555. #define PCI_INIT_WIN_CFG_WIN2_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
  556. #define PCI_INIT_WIN_CFG_WIN2_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
  557. /* PCI Initiator Control Register (PCIICR) */
  558. #define PCI_INIT_CTRL_REE_SHIFT 26
  559. #define PCI_INIT_CTRL_IAE_SHIFT 25
  560. #define PCI_INIT_CTRL_TAE_SHIFT 24
  561. #define PCI_INIT_CTRL_MAX_RETRIES_SHIFT 0
  562. #define PCI_INIT_CTRL_MAX_RETRIES_MASK 0xff
  563. #define PCI_INIT_CTRL_REE (1<<PCI_INIT_CTRL_REE_SHIFT)
  564. #define PCI_INIT_CTRL_IAE (1<<PCI_INIT_CTRL_IAE_SHIFT)
  565. #define PCI_INIT_CTRL_TAE (1<<PCI_INIT_CTRL_TAE_SHIFT)
  566. /* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
  567. #define PCI_STAT_CMD_PE_SHIFT 31
  568. #define PCI_STAT_CMD_SE_SHIFT 30
  569. #define PCI_STAT_CMD_MA_SHIFT 29
  570. #define PCI_STAT_CMD_TR_SHIFT 28
  571. #define PCI_STAT_CMD_TS_SHIFT 27
  572. #define PCI_STAT_CMD_DT_SHIFT 25
  573. #define PCI_STAT_CMD_DT_MASK 0x3
  574. #define PCI_STAT_CMD_DP_SHIFT 24
  575. #define PCI_STAT_CMD_FC_SHIFT 23
  576. #define PCI_STAT_CMD_R_SHIFT 22
  577. #define PCI_STAT_CMD_66M_SHIFT 21
  578. #define PCI_STAT_CMD_C_SHIFT 20
  579. #define PCI_STAT_CMD_F_SHIFT 9
  580. #define PCI_STAT_CMD_S_SHIFT 8
  581. #define PCI_STAT_CMD_ST_SHIFT 7
  582. #define PCI_STAT_CMD_PER_SHIFT 6
  583. #define PCI_STAT_CMD_V_SHIFT 5
  584. #define PCI_STAT_CMD_MW_SHIFT 4
  585. #define PCI_STAT_CMD_SP_SHIFT 3
  586. #define PCI_STAT_CMD_B_SHIFT 2
  587. #define PCI_STAT_CMD_M_SHIFT 1
  588. #define PCI_STAT_CMD_IO_SHIFT 0
  589. #define PCI_STAT_CMD_PE (1<<PCI_STAT_CMD_PE_SHIFT)
  590. #define PCI_STAT_CMD_SE (1<<PCI_STAT_CMD_SE_SHIFT)
  591. #define PCI_STAT_CMD_MA (1<<PCI_STAT_CMD_MA_SHIFT)
  592. #define PCI_STAT_CMD_TR (1<<PCI_STAT_CMD_TR_SHIFT)
  593. #define PCI_STAT_CMD_TS (1<<PCI_STAT_CMD_TS_SHIFT)
  594. #define PCI_STAT_CMD_DP (1<<PCI_STAT_CMD_DP_SHIFT)
  595. #define PCI_STAT_CMD_FC (1<<PCI_STAT_CMD_FC_SHIFT)
  596. #define PCI_STAT_CMD_R (1<<PCI_STAT_CMD_R_SHIFT)
  597. #define PCI_STAT_CMD_66M (1<<PCI_STAT_CMD_66M_SHIFT)
  598. #define PCI_STAT_CMD_C (1<<PCI_STAT_CMD_C_SHIFT)
  599. #define PCI_STAT_CMD_F (1<<PCI_STAT_CMD_F_SHIFT)
  600. #define PCI_STAT_CMD_S (1<<PCI_STAT_CMD_S_SHIFT)
  601. #define PCI_STAT_CMD_ST (1<<PCI_STAT_CMD_ST_SHIFT)
  602. #define PCI_STAT_CMD_PER (1<<PCI_STAT_CMD_PER_SHIFT)
  603. #define PCI_STAT_CMD_V (1<<PCI_STAT_CMD_V_SHIFT)
  604. #define PCI_STAT_CMD_MW (1<<PCI_STAT_CMD_MW_SHIFT)
  605. #define PCI_STAT_CMD_SP (1<<PCI_STAT_CMD_SP_SHIFT)
  606. #define PCI_STAT_CMD_B (1<<PCI_STAT_CMD_B_SHIFT)
  607. #define PCI_STAT_CMD_M (1<<PCI_STAT_CMD_M_SHIFT)
  608. #define PCI_STAT_CMD_IO (1<<PCI_STAT_CMD_IO_SHIFT)
  609. /* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
  610. #define PCI_CFG1_HT_SHIFT 16
  611. #define PCI_CFG1_HT_MASK 0xff
  612. #define PCI_CFG1_LT_SHIFT 8
  613. #define PCI_CFG1_LT_MASK 0xff
  614. #define PCI_CFG1_CLS_SHIFT 0
  615. #define PCI_CFG1_CLS_MASK 0xf
  616. /* function prototypes */
  617. void loadtask(int basetask, int tasks);
  618. u32 dramSetup(void);
  619. #if defined(CONFIG_PSC_CONSOLE)
  620. int psc_serial_init (void);
  621. void psc_serial_putc(const char c);
  622. void psc_serial_puts (const char *s);
  623. int psc_serial_getc(void);
  624. int psc_serial_tstc(void);
  625. void psc_serial_setbrg(void);
  626. #endif
  627. #if defined (CONFIG_EXTUART_CONSOLE)
  628. int ext_serial_init (void);
  629. void ext_serial_putc(const char c);
  630. void ext_serial_puts (const char *s);
  631. int ext_serial_getc(void);
  632. int ext_serial_tstc(void);
  633. void ext_serial_setbrg(void);
  634. #endif
  635. #endif /* __ASSEMBLY__ */
  636. #endif /* __MPC8220_H__ */