mpc5xxx.h 35 KB

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  1. /*
  2. * include/asm-ppc/mpc5xxx.h
  3. *
  4. * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
  5. * embedded cpu chips
  6. *
  7. * 2003 (c) MontaVista, Software, Inc.
  8. * Author: Dale Farnsworth <dfarnsworth@mvista.com>
  9. *
  10. * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef __ASMPPC_MPC5XXX_H
  31. #define __ASMPPC_MPC5XXX_H
  32. #include <asm/types.h>
  33. /* Processor name */
  34. #if defined(CONFIG_MPC5200)
  35. #define CPU_ID_STR "MPC5200"
  36. #elif defined(CONFIG_MGT5100)
  37. #define CPU_ID_STR "MGT5100"
  38. #endif
  39. /* Exception offsets (PowerPC standard) */
  40. #define EXC_OFF_SYS_RESET 0x0100
  41. #define _START_OFFSET EXC_OFF_SYS_RESET
  42. /* useful macros for manipulating CSx_START/STOP */
  43. #if defined(CONFIG_MGT5100)
  44. #define START_REG(start) ((start) >> 15)
  45. #define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
  46. #elif defined(CONFIG_MPC5200)
  47. #define START_REG(start) ((start) >> 16)
  48. #define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
  49. #endif
  50. /* Internal memory map */
  51. #define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004)
  52. #define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008)
  53. #define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c)
  54. #define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010)
  55. #define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014)
  56. #define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018)
  57. #define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c)
  58. #define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020)
  59. #define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024)
  60. #define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028)
  61. #define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c)
  62. #define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030)
  63. #define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c)
  64. #define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050)
  65. #define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054)
  66. #if defined(CONFIG_MGT5100)
  67. #define MPC5XXX_SDRAM_START (CONFIG_SYS_MBAR + 0x0034)
  68. #define MPC5XXX_SDRAM_STOP (CONFIG_SYS_MBAR + 0x0038)
  69. #define MPC5XXX_PCI1_START (CONFIG_SYS_MBAR + 0x003c)
  70. #define MPC5XXX_PCI1_STOP (CONFIG_SYS_MBAR + 0x0040)
  71. #define MPC5XXX_PCI2_START (CONFIG_SYS_MBAR + 0x0044)
  72. #define MPC5XXX_PCI2_STOP (CONFIG_SYS_MBAR + 0x0048)
  73. #elif defined(CONFIG_MPC5200)
  74. #define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058)
  75. #define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c)
  76. #define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060)
  77. #define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064)
  78. #define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034)
  79. #define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038)
  80. #endif
  81. #define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100)
  82. #define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200)
  83. #define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300)
  84. #define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500)
  85. #define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600)
  86. #define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00)
  87. #define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00)
  88. #define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00)
  89. #define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00)
  90. #define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000)
  91. #define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200)
  92. #define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00)
  93. #if defined(CONFIG_MGT5100)
  94. #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
  95. #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2400)
  96. #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2800)
  97. #elif defined(CONFIG_MPC5200)
  98. #define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000)
  99. #define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200)
  100. #define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400)
  101. #define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600)
  102. #define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800)
  103. #define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00)
  104. #endif
  105. #define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000)
  106. #define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00)
  107. #define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00)
  108. #define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40)
  109. #if defined(CONFIG_MGT5100)
  110. #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x4000)
  111. #define MPC5XXX_SRAM_SIZE (8*1024)
  112. #elif defined(CONFIG_MPC5200)
  113. #define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000)
  114. #define MPC5XXX_SRAM_SIZE (16*1024)
  115. #endif
  116. /* SDRAM Controller */
  117. #define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
  118. #define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
  119. #define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
  120. #define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
  121. #if defined(CONFIG_MGT5100)
  122. #define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
  123. #endif
  124. #define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090)
  125. /* Clock Distribution Module */
  126. #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
  127. #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
  128. #define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008)
  129. #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
  130. #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
  131. #define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014)
  132. #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
  133. /* Local Plus Bus interface */
  134. #define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
  135. #define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
  136. #define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
  137. #define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
  138. #define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
  139. #define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
  140. #define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
  141. #define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
  142. #define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
  143. #if defined(CONFIG_MPC5200)
  144. #define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
  145. #define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
  146. #define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
  147. #define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
  148. #endif
  149. #if defined(CONFIG_MPC5200)
  150. /* XLB Arbiter registers */
  151. #define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
  152. #define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
  153. #define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
  154. #endif
  155. /* GPIO registers */
  156. #define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
  157. /* Standard GPIO registers (simple, output only and simple interrupt */
  158. #define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
  159. #define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008)
  160. #define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c)
  161. #define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010)
  162. #define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014)
  163. #define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018)
  164. #define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C)
  165. #define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020)
  166. #define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024)
  167. #define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028)
  168. #define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C)
  169. #define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030)
  170. #define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034)
  171. #define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038)
  172. #define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C)
  173. /* WakeUp GPIO registers */
  174. #define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
  175. #define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
  176. #define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
  177. #define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c)
  178. #define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020)
  179. /* GPIO pins */
  180. #define GPIO_WKUP_7 0x80000000UL
  181. #define GPIO_PSC6_0 0x10000000UL
  182. #define GPIO_PSC3_9 0x04000000UL
  183. #define GPIO_PSC1_4 0x01000000UL
  184. #define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL
  185. #define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL
  186. #define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL
  187. #define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL
  188. #define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL
  189. #define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL
  190. #define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL
  191. #define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL
  192. #define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL
  193. #define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL
  194. #define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL
  195. #define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL
  196. #define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL
  197. #define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL
  198. #define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL
  199. #define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL
  200. #define MPC5XXX_GPIO_SINT_ETH_16 0x80
  201. #define MPC5XXX_GPIO_SINT_ETH_15 0x40
  202. #define MPC5XXX_GPIO_SINT_ETH_14 0x20
  203. #define MPC5XXX_GPIO_SINT_ETH_13 0x10
  204. #define MPC5XXX_GPIO_SINT_USB1_9 0x08
  205. #define MPC5XXX_GPIO_SINT_PSC3_8 0x04
  206. #define MPC5XXX_GPIO_SINT_PSC3_5 0x02
  207. #define MPC5XXX_GPIO_SINT_PSC3_4 0x01
  208. #define MPC5XXX_GPIO_WKUP_7 0x80
  209. #define MPC5XXX_GPIO_WKUP_6 0x40
  210. #define MPC5XXX_GPIO_WKUP_PSC6_1 0x20
  211. #define MPC5XXX_GPIO_WKUP_PSC6_0 0x10
  212. #define MPC5XXX_GPIO_WKUP_ETH17 0x08
  213. #define MPC5XXX_GPIO_WKUP_PSC3_9 0x04
  214. #define MPC5XXX_GPIO_WKUP_PSC2_4 0x02
  215. #define MPC5XXX_GPIO_WKUP_PSC1_4 0x01
  216. /* PCI registers */
  217. #define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
  218. #define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
  219. #define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
  220. #define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
  221. #if defined(CONFIG_MGT5100)
  222. #define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
  223. #define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
  224. #define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
  225. #define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
  226. #define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
  227. #define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
  228. #elif defined(CONFIG_MPC5200)
  229. #define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
  230. #define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
  231. #define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
  232. #define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
  233. #define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
  234. #define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
  235. #define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
  236. #define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
  237. #define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
  238. #define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
  239. #define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
  240. #define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
  241. #endif
  242. /* Interrupt Controller registers */
  243. #define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
  244. #define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
  245. #define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
  246. #define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
  247. #define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
  248. #define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
  249. #define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
  250. #define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
  251. #define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
  252. #define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
  253. #define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
  254. #define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
  255. #define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
  256. #define NR_IRQS 64
  257. /* IRQ mapping - these are our logical IRQ numbers */
  258. #define MPC5XXX_CRIT_IRQ_NUM 4
  259. #define MPC5XXX_MAIN_IRQ_NUM 17
  260. #define MPC5XXX_SDMA_IRQ_NUM 17
  261. #define MPC5XXX_PERP_IRQ_NUM 23
  262. #define MPC5XXX_CRIT_IRQ_BASE 1
  263. #define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
  264. #define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
  265. #define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
  266. #define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
  267. #define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
  268. #define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
  269. #define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
  270. #define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
  271. #define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
  272. #define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
  273. #define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
  274. #define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
  275. #define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
  276. #define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
  277. #define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
  278. #define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
  279. #define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
  280. #define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
  281. #define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
  282. #define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
  283. #define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
  284. #define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
  285. #define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
  286. #define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
  287. #define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
  288. #define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
  289. #define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
  290. #define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
  291. #define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
  292. #define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
  293. #define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
  294. #define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
  295. #define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
  296. #define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
  297. #define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
  298. #define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
  299. #define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
  300. #define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
  301. #define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
  302. #define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
  303. #define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
  304. #define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
  305. #define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
  306. #define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
  307. #define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
  308. #define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
  309. /* General Purpose Timers registers */
  310. #define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
  311. #define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
  312. #define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
  313. #define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
  314. #define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
  315. #define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
  316. #define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
  317. #define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
  318. #define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
  319. #define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
  320. #define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
  321. #define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
  322. #define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
  323. #define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
  324. #define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
  325. #define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
  326. #define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
  327. #define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
  328. #define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
  329. #define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
  330. #define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
  331. #define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
  332. #define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
  333. #define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
  334. #define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
  335. #define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)
  336. /* ATA registers */
  337. #define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
  338. #define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
  339. #define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
  340. #define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
  341. /* I2Cn control register bits */
  342. #define I2C_EN 0x80
  343. #define I2C_IEN 0x40
  344. #define I2C_STA 0x20
  345. #define I2C_TX 0x10
  346. #define I2C_TXAK 0x08
  347. #define I2C_RSTA 0x04
  348. #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
  349. /* I2Cn status register bits */
  350. #define I2C_CF 0x80
  351. #define I2C_AAS 0x40
  352. #define I2C_BB 0x20
  353. #define I2C_AL 0x10
  354. #define I2C_SRW 0x04
  355. #define I2C_IF 0x02
  356. #define I2C_RXAK 0x01
  357. /* SPI control register 1 bits */
  358. #define SPI_CR_LSBFE 0x01
  359. #define SPI_CR_SSOE 0x02
  360. #define SPI_CR_CPHA 0x04
  361. #define SPI_CR_CPOL 0x08
  362. #define SPI_CR_MSTR 0x10
  363. #define SPI_CR_SWOM 0x20
  364. #define SPI_CR_SPE 0x40
  365. #define SPI_CR_SPIE 0x80
  366. /* SPI status register bits */
  367. #define SPI_SR_MODF 0x10
  368. #define SPI_SR_WCOL 0x40
  369. #define SPI_SR_SPIF 0x80
  370. /* SPI port data register bits */
  371. #define SPI_PDR_SS 0x08
  372. /* Programmable Serial Controller (PSC) status register bits */
  373. #define PSC_SR_CDE 0x0080
  374. #define PSC_SR_RXRDY 0x0100
  375. #define PSC_SR_RXFULL 0x0200
  376. #define PSC_SR_TXRDY 0x0400
  377. #define PSC_SR_TXEMP 0x0800
  378. #define PSC_SR_OE 0x1000
  379. #define PSC_SR_PE 0x2000
  380. #define PSC_SR_FE 0x4000
  381. #define PSC_SR_RB 0x8000
  382. /* PSC Command values */
  383. #define PSC_RX_ENABLE 0x0001
  384. #define PSC_RX_DISABLE 0x0002
  385. #define PSC_TX_ENABLE 0x0004
  386. #define PSC_TX_DISABLE 0x0008
  387. #define PSC_SEL_MODE_REG_1 0x0010
  388. #define PSC_RST_RX 0x0020
  389. #define PSC_RST_TX 0x0030
  390. #define PSC_RST_ERR_STAT 0x0040
  391. #define PSC_RST_BRK_CHG_INT 0x0050
  392. #define PSC_START_BRK 0x0060
  393. #define PSC_STOP_BRK 0x0070
  394. /* PSC Rx FIFO status bits */
  395. #define PSC_RX_FIFO_ERR 0x0040
  396. #define PSC_RX_FIFO_UF 0x0020
  397. #define PSC_RX_FIFO_OF 0x0010
  398. #define PSC_RX_FIFO_FR 0x0008
  399. #define PSC_RX_FIFO_FULL 0x0004
  400. #define PSC_RX_FIFO_ALARM 0x0002
  401. #define PSC_RX_FIFO_EMPTY 0x0001
  402. /* PSC interrupt mask bits */
  403. #define PSC_IMR_TXRDY 0x0100
  404. #define PSC_IMR_RXRDY 0x0200
  405. #define PSC_IMR_DB 0x0400
  406. #define PSC_IMR_IPC 0x8000
  407. /* PSC input port change bits */
  408. #define PSC_IPCR_CTS 0x01
  409. #define PSC_IPCR_DCD 0x02
  410. /* PSC mode fields */
  411. #define PSC_MODE_5_BITS 0x00
  412. #define PSC_MODE_6_BITS 0x01
  413. #define PSC_MODE_7_BITS 0x02
  414. #define PSC_MODE_8_BITS 0x03
  415. #define PSC_MODE_PAREVEN 0x00
  416. #define PSC_MODE_PARODD 0x04
  417. #define PSC_MODE_PARFORCE 0x08
  418. #define PSC_MODE_PARNONE 0x10
  419. #define PSC_MODE_ERR 0x20
  420. #define PSC_MODE_FFULL 0x40
  421. #define PSC_MODE_RXRTS 0x80
  422. #define PSC_MODE_ONE_STOP_5_BITS 0x00
  423. #define PSC_MODE_ONE_STOP 0x07
  424. #define PSC_MODE_TWO_STOP 0x0f
  425. /* ATA config fields */
  426. #define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
  427. reset */
  428. #define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
  429. #define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
  430. in PIO */
  431. #define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
  432. IORDY protocol */
  433. #ifndef __ASSEMBLY__
  434. /* Memory map registers */
  435. struct mpc5xxx_mmap_ctl {
  436. volatile u32 mbar;
  437. volatile u32 cs0_start; /* 0x0004 */
  438. volatile u32 cs0_stop;
  439. volatile u32 cs1_start; /* 0x000c */
  440. volatile u32 cs1_stop;
  441. volatile u32 cs2_start; /* 0x0014 */
  442. volatile u32 cs2_stop;
  443. volatile u32 cs3_start; /* 0x001c */
  444. volatile u32 cs3_stop;
  445. volatile u32 cs4_start; /* 0x0024 */
  446. volatile u32 cs4_stop;
  447. volatile u32 cs5_start; /* 0x002c */
  448. volatile u32 cs5_stop;
  449. #if defined(CONFIG_MGT5100)
  450. volatile u32 sdram_start; /* 0x0034 */
  451. volatile u32 sdram_stop; /* 0x0038 */
  452. volatile u32 pci1_start; /* 0x003c */
  453. volatile u32 pci1_stop; /* 0x0040 */
  454. volatile u32 pci2_start; /* 0x0044 */
  455. volatile u32 pci2_stop; /* 0x0048 */
  456. #elif defined(CONFIG_MPC5200)
  457. volatile u32 sdram0; /* 0x0034 */
  458. volatile u32 sdram1; /* 0x0038 */
  459. volatile u32 dummy1[4]; /* 0x003c */
  460. #endif
  461. volatile u32 boot_start; /* 0x004c */
  462. volatile u32 boot_stop;
  463. #if defined(CONFIG_MGT5100)
  464. volatile u32 addecr; /* 0x0054 */
  465. #elif defined(CONFIG_MPC5200)
  466. volatile u32 ipbi_ws_ctrl; /* 0x0054 */
  467. #endif
  468. #if defined(CONFIG_MPC5200)
  469. volatile u32 cs6_start; /* 0x0058 */
  470. volatile u32 cs6_stop;
  471. volatile u32 cs7_start; /* 0x0060 */
  472. volatile u32 cs7_stop;
  473. #endif
  474. };
  475. /* Clock distribution module */
  476. struct mpc5xxx_cdm {
  477. volatile u32 jtagid; /* 0x0000 */
  478. volatile u32 porcfg;
  479. volatile u32 brdcrmb; /* 0x0008 */
  480. volatile u32 cfg;
  481. volatile u32 fourtyeight_fdc;/* 0x0010 */
  482. volatile u32 clock_enable;
  483. volatile u32 system_osc; /* 0x0018 */
  484. volatile u32 ccscr;
  485. volatile u32 sreset; /* 0x0020 */
  486. volatile u32 pll_status;
  487. volatile u32 psc1_mccr; /* 0x0028 */
  488. volatile u32 psc2_mccr;
  489. volatile u32 psc3_mccr; /* 0x0030 */
  490. volatile u32 psc6_mccr;
  491. };
  492. /* SDRAM controller */
  493. struct mpc5xxx_sdram {
  494. volatile u32 mode;
  495. volatile u32 ctrl;
  496. volatile u32 config1;
  497. volatile u32 config2;
  498. #if defined(CONFIG_MGT5100)
  499. volatile u32 xlbsel;
  500. volatile u32 dummy[31];
  501. #else
  502. volatile u32 dummy[32];
  503. #endif
  504. volatile u32 sdelay;
  505. };
  506. struct mpc5xxx_lpb {
  507. volatile u32 cs0_cfg;
  508. volatile u32 cs1_cfg;
  509. volatile u32 cs2_cfg;
  510. volatile u32 cs3_cfg;
  511. volatile u32 cs4_cfg;
  512. volatile u32 cs5_cfg;
  513. volatile u32 cs_ctrl;
  514. volatile u32 cs_status;
  515. #if defined(CONFIG_MPC5200)
  516. volatile u32 cs6_cfg;
  517. volatile u32 cs7_cfg;
  518. volatile u32 cs_burst;
  519. volatile u32 cs_deadcycle;
  520. #endif
  521. };
  522. struct mpc5xxx_psc {
  523. volatile u8 mode; /* PSC + 0x00 */
  524. volatile u8 reserved0[3];
  525. union { /* PSC + 0x04 */
  526. volatile u16 status;
  527. volatile u16 clock_select;
  528. } sr_csr;
  529. #define psc_status sr_csr.status
  530. #define psc_clock_select sr_csr.clock_select
  531. volatile u16 reserved1;
  532. volatile u8 command; /* PSC + 0x08 */
  533. volatile u8 reserved2[3];
  534. union { /* PSC + 0x0c */
  535. volatile u8 buffer_8;
  536. volatile u16 buffer_16;
  537. volatile u32 buffer_32;
  538. } buffer;
  539. #define psc_buffer_8 buffer.buffer_8
  540. #define psc_buffer_16 buffer.buffer_16
  541. #define psc_buffer_32 buffer.buffer_32
  542. union { /* PSC + 0x10 */
  543. volatile u8 ipcr;
  544. volatile u8 acr;
  545. } ipcr_acr;
  546. #define psc_ipcr ipcr_acr.ipcr
  547. #define psc_acr ipcr_acr.acr
  548. volatile u8 reserved3[3];
  549. union { /* PSC + 0x14 */
  550. volatile u16 isr;
  551. volatile u16 imr;
  552. } isr_imr;
  553. #define psc_isr isr_imr.isr
  554. #define psc_imr isr_imr.imr
  555. volatile u16 reserved4;
  556. volatile u8 ctur; /* PSC + 0x18 */
  557. volatile u8 reserved5[3];
  558. volatile u8 ctlr; /* PSC + 0x1c */
  559. volatile u8 reserved6[3];
  560. volatile u16 ccr; /* PSC + 0x20 */
  561. volatile u8 reserved7[14];
  562. volatile u8 ivr; /* PSC + 0x30 */
  563. volatile u8 reserved8[3];
  564. volatile u8 ip; /* PSC + 0x34 */
  565. volatile u8 reserved9[3];
  566. volatile u8 op1; /* PSC + 0x38 */
  567. volatile u8 reserved10[3];
  568. volatile u8 op0; /* PSC + 0x3c */
  569. volatile u8 reserved11[3];
  570. volatile u32 sicr; /* PSC + 0x40 */
  571. volatile u8 ircr1; /* PSC + 0x44 */
  572. volatile u8 reserved12[3];
  573. volatile u8 ircr2; /* PSC + 0x44 */
  574. volatile u8 reserved13[3];
  575. volatile u8 irsdr; /* PSC + 0x4c */
  576. volatile u8 reserved14[3];
  577. volatile u8 irmdr; /* PSC + 0x50 */
  578. volatile u8 reserved15[3];
  579. volatile u8 irfdr; /* PSC + 0x54 */
  580. volatile u8 reserved16[3];
  581. volatile u16 rfnum; /* PSC + 0x58 */
  582. volatile u16 reserved17;
  583. volatile u16 tfnum; /* PSC + 0x5c */
  584. volatile u16 reserved18;
  585. volatile u32 rfdata; /* PSC + 0x60 */
  586. volatile u16 rfstat; /* PSC + 0x64 */
  587. volatile u16 reserved20;
  588. volatile u8 rfcntl; /* PSC + 0x68 */
  589. volatile u8 reserved21[5];
  590. volatile u16 rfalarm; /* PSC + 0x6e */
  591. volatile u16 reserved22;
  592. volatile u16 rfrptr; /* PSC + 0x72 */
  593. volatile u16 reserved23;
  594. volatile u16 rfwptr; /* PSC + 0x76 */
  595. volatile u16 reserved24;
  596. volatile u16 rflrfptr; /* PSC + 0x7a */
  597. volatile u16 reserved25;
  598. volatile u16 rflwfptr; /* PSC + 0x7e */
  599. volatile u32 tfdata; /* PSC + 0x80 */
  600. volatile u16 tfstat; /* PSC + 0x84 */
  601. volatile u16 reserved26;
  602. volatile u8 tfcntl; /* PSC + 0x88 */
  603. volatile u8 reserved27[5];
  604. volatile u16 tfalarm; /* PSC + 0x8e */
  605. volatile u16 reserved28;
  606. volatile u16 tfrptr; /* PSC + 0x92 */
  607. volatile u16 reserved29;
  608. volatile u16 tfwptr; /* PSC + 0x96 */
  609. volatile u16 reserved30;
  610. volatile u16 tflrfptr; /* PSC + 0x9a */
  611. volatile u16 reserved31;
  612. volatile u16 tflwfptr; /* PSC + 0x9e */
  613. };
  614. struct mpc5xxx_intr {
  615. volatile u32 per_mask; /* INTR + 0x00 */
  616. volatile u32 per_pri1; /* INTR + 0x04 */
  617. volatile u32 per_pri2; /* INTR + 0x08 */
  618. volatile u32 per_pri3; /* INTR + 0x0c */
  619. volatile u32 ctrl; /* INTR + 0x10 */
  620. volatile u32 main_mask; /* INTR + 0x14 */
  621. volatile u32 main_pri1; /* INTR + 0x18 */
  622. volatile u32 main_pri2; /* INTR + 0x1c */
  623. volatile u32 reserved1; /* INTR + 0x20 */
  624. volatile u32 enc_status; /* INTR + 0x24 */
  625. volatile u32 crit_status; /* INTR + 0x28 */
  626. volatile u32 main_status; /* INTR + 0x2c */
  627. volatile u32 per_status; /* INTR + 0x30 */
  628. volatile u32 reserved2; /* INTR + 0x34 */
  629. volatile u32 per_error; /* INTR + 0x38 */
  630. };
  631. struct mpc5xxx_gpio {
  632. volatile u32 port_config; /* GPIO + 0x00 */
  633. volatile u32 simple_gpioe; /* GPIO + 0x04 */
  634. volatile u32 simple_ode; /* GPIO + 0x08 */
  635. volatile u32 simple_ddr; /* GPIO + 0x0c */
  636. volatile u32 simple_dvo; /* GPIO + 0x10 */
  637. volatile u32 simple_ival; /* GPIO + 0x14 */
  638. volatile u8 outo_gpioe; /* GPIO + 0x18 */
  639. volatile u8 reserved1[3]; /* GPIO + 0x19 */
  640. volatile u8 outo_dvo; /* GPIO + 0x1c */
  641. volatile u8 reserved2[3]; /* GPIO + 0x1d */
  642. volatile u8 sint_gpioe; /* GPIO + 0x20 */
  643. volatile u8 reserved3[3]; /* GPIO + 0x21 */
  644. volatile u8 sint_ode; /* GPIO + 0x24 */
  645. volatile u8 reserved4[3]; /* GPIO + 0x25 */
  646. volatile u8 sint_ddr; /* GPIO + 0x28 */
  647. volatile u8 reserved5[3]; /* GPIO + 0x29 */
  648. volatile u8 sint_dvo; /* GPIO + 0x2c */
  649. volatile u8 reserved6[3]; /* GPIO + 0x2d */
  650. volatile u8 sint_inten; /* GPIO + 0x30 */
  651. volatile u8 reserved7[3]; /* GPIO + 0x31 */
  652. volatile u16 sint_itype; /* GPIO + 0x34 */
  653. volatile u16 reserved8; /* GPIO + 0x36 */
  654. volatile u8 gpio_control; /* GPIO + 0x38 */
  655. volatile u8 reserved9[3]; /* GPIO + 0x39 */
  656. volatile u8 sint_istat; /* GPIO + 0x3c */
  657. volatile u8 sint_ival; /* GPIO + 0x3d */
  658. volatile u8 bus_errs; /* GPIO + 0x3e */
  659. volatile u8 reserved10; /* GPIO + 0x3f */
  660. };
  661. struct mpc5xxx_wu_gpio {
  662. volatile u8 enable; /* WU_GPIO + 0x00 */
  663. volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */
  664. volatile u8 ode; /* WU_GPIO + 0x04 */
  665. volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */
  666. volatile u8 ddr; /* WU_GPIO + 0x08 */
  667. volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */
  668. volatile u8 dvo; /* WU_GPIO + 0x0c */
  669. volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */
  670. volatile u8 inten; /* WU_GPIO + 0x10 */
  671. volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */
  672. volatile u8 iinten; /* WU_GPIO + 0x14 */
  673. volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */
  674. volatile u16 itype; /* WU_GPIO + 0x18 */
  675. volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */
  676. volatile u8 master_enable; /* WU_GPIO + 0x1c */
  677. volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */
  678. volatile u8 ival; /* WU_GPIO + 0x20 */
  679. volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */
  680. volatile u8 status; /* WU_GPIO + 0x24 */
  681. volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */
  682. };
  683. struct mpc5xxx_sdma {
  684. volatile u32 taskBar; /* SDMA + 0x00 */
  685. volatile u32 currentPointer; /* SDMA + 0x04 */
  686. volatile u32 endPointer; /* SDMA + 0x08 */
  687. volatile u32 variablePointer; /* SDMA + 0x0c */
  688. volatile u8 IntVect1; /* SDMA + 0x10 */
  689. volatile u8 IntVect2; /* SDMA + 0x11 */
  690. volatile u16 PtdCntrl; /* SDMA + 0x12 */
  691. volatile u32 IntPend; /* SDMA + 0x14 */
  692. volatile u32 IntMask; /* SDMA + 0x18 */
  693. volatile u16 tcr_0; /* SDMA + 0x1c */
  694. volatile u16 tcr_1; /* SDMA + 0x1e */
  695. volatile u16 tcr_2; /* SDMA + 0x20 */
  696. volatile u16 tcr_3; /* SDMA + 0x22 */
  697. volatile u16 tcr_4; /* SDMA + 0x24 */
  698. volatile u16 tcr_5; /* SDMA + 0x26 */
  699. volatile u16 tcr_6; /* SDMA + 0x28 */
  700. volatile u16 tcr_7; /* SDMA + 0x2a */
  701. volatile u16 tcr_8; /* SDMA + 0x2c */
  702. volatile u16 tcr_9; /* SDMA + 0x2e */
  703. volatile u16 tcr_a; /* SDMA + 0x30 */
  704. volatile u16 tcr_b; /* SDMA + 0x32 */
  705. volatile u16 tcr_c; /* SDMA + 0x34 */
  706. volatile u16 tcr_d; /* SDMA + 0x36 */
  707. volatile u16 tcr_e; /* SDMA + 0x38 */
  708. volatile u16 tcr_f; /* SDMA + 0x3a */
  709. volatile u8 IPR0; /* SDMA + 0x3c */
  710. volatile u8 IPR1; /* SDMA + 0x3d */
  711. volatile u8 IPR2; /* SDMA + 0x3e */
  712. volatile u8 IPR3; /* SDMA + 0x3f */
  713. volatile u8 IPR4; /* SDMA + 0x40 */
  714. volatile u8 IPR5; /* SDMA + 0x41 */
  715. volatile u8 IPR6; /* SDMA + 0x42 */
  716. volatile u8 IPR7; /* SDMA + 0x43 */
  717. volatile u8 IPR8; /* SDMA + 0x44 */
  718. volatile u8 IPR9; /* SDMA + 0x45 */
  719. volatile u8 IPR10; /* SDMA + 0x46 */
  720. volatile u8 IPR11; /* SDMA + 0x47 */
  721. volatile u8 IPR12; /* SDMA + 0x48 */
  722. volatile u8 IPR13; /* SDMA + 0x49 */
  723. volatile u8 IPR14; /* SDMA + 0x4a */
  724. volatile u8 IPR15; /* SDMA + 0x4b */
  725. volatile u8 IPR16; /* SDMA + 0x4c */
  726. volatile u8 IPR17; /* SDMA + 0x4d */
  727. volatile u8 IPR18; /* SDMA + 0x4e */
  728. volatile u8 IPR19; /* SDMA + 0x4f */
  729. volatile u8 IPR20; /* SDMA + 0x50 */
  730. volatile u8 IPR21; /* SDMA + 0x51 */
  731. volatile u8 IPR22; /* SDMA + 0x52 */
  732. volatile u8 IPR23; /* SDMA + 0x53 */
  733. volatile u8 IPR24; /* SDMA + 0x54 */
  734. volatile u8 IPR25; /* SDMA + 0x55 */
  735. volatile u8 IPR26; /* SDMA + 0x56 */
  736. volatile u8 IPR27; /* SDMA + 0x57 */
  737. volatile u8 IPR28; /* SDMA + 0x58 */
  738. volatile u8 IPR29; /* SDMA + 0x59 */
  739. volatile u8 IPR30; /* SDMA + 0x5a */
  740. volatile u8 IPR31; /* SDMA + 0x5b */
  741. volatile u32 res1; /* SDMA + 0x5c */
  742. volatile u32 res2; /* SDMA + 0x60 */
  743. volatile u32 res3; /* SDMA + 0x64 */
  744. volatile u32 MDEDebug; /* SDMA + 0x68 */
  745. volatile u32 ADSDebug; /* SDMA + 0x6c */
  746. volatile u32 Value1; /* SDMA + 0x70 */
  747. volatile u32 Value2; /* SDMA + 0x74 */
  748. volatile u32 Control; /* SDMA + 0x78 */
  749. volatile u32 Status; /* SDMA + 0x7c */
  750. volatile u32 EU00; /* SDMA + 0x80 */
  751. volatile u32 EU01; /* SDMA + 0x84 */
  752. volatile u32 EU02; /* SDMA + 0x88 */
  753. volatile u32 EU03; /* SDMA + 0x8c */
  754. volatile u32 EU04; /* SDMA + 0x90 */
  755. volatile u32 EU05; /* SDMA + 0x94 */
  756. volatile u32 EU06; /* SDMA + 0x98 */
  757. volatile u32 EU07; /* SDMA + 0x9c */
  758. volatile u32 EU10; /* SDMA + 0xa0 */
  759. volatile u32 EU11; /* SDMA + 0xa4 */
  760. volatile u32 EU12; /* SDMA + 0xa8 */
  761. volatile u32 EU13; /* SDMA + 0xac */
  762. volatile u32 EU14; /* SDMA + 0xb0 */
  763. volatile u32 EU15; /* SDMA + 0xb4 */
  764. volatile u32 EU16; /* SDMA + 0xb8 */
  765. volatile u32 EU17; /* SDMA + 0xbc */
  766. volatile u32 EU20; /* SDMA + 0xc0 */
  767. volatile u32 EU21; /* SDMA + 0xc4 */
  768. volatile u32 EU22; /* SDMA + 0xc8 */
  769. volatile u32 EU23; /* SDMA + 0xcc */
  770. volatile u32 EU24; /* SDMA + 0xd0 */
  771. volatile u32 EU25; /* SDMA + 0xd4 */
  772. volatile u32 EU26; /* SDMA + 0xd8 */
  773. volatile u32 EU27; /* SDMA + 0xdc */
  774. volatile u32 EU30; /* SDMA + 0xe0 */
  775. volatile u32 EU31; /* SDMA + 0xe4 */
  776. volatile u32 EU32; /* SDMA + 0xe8 */
  777. volatile u32 EU33; /* SDMA + 0xec */
  778. volatile u32 EU34; /* SDMA + 0xf0 */
  779. volatile u32 EU35; /* SDMA + 0xf4 */
  780. volatile u32 EU36; /* SDMA + 0xf8 */
  781. volatile u32 EU37; /* SDMA + 0xfc */
  782. };
  783. struct mpc5xxx_i2c {
  784. volatile u32 madr; /* I2Cn + 0x00 */
  785. volatile u32 mfdr; /* I2Cn + 0x04 */
  786. volatile u32 mcr; /* I2Cn + 0x08 */
  787. volatile u32 msr; /* I2Cn + 0x0C */
  788. volatile u32 mdr; /* I2Cn + 0x10 */
  789. };
  790. struct mpc5xxx_spi {
  791. volatile u8 cr1; /* SPI + 0x0F00 */
  792. volatile u8 cr2; /* SPI + 0x0F01 */
  793. volatile u8 reserved1[2];
  794. volatile u8 brr; /* SPI + 0x0F04 */
  795. volatile u8 sr; /* SPI + 0x0F05 */
  796. volatile u8 reserved2[3];
  797. volatile u8 dr; /* SPI + 0x0F09 */
  798. volatile u8 reserved3[3];
  799. volatile u8 pdr; /* SPI + 0x0F0D */
  800. volatile u8 reserved4[2];
  801. volatile u8 ddr; /* SPI + 0x0F10 */
  802. };
  803. struct mpc5xxx_gpt {
  804. volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */
  805. volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */
  806. volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */
  807. volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */
  808. };
  809. struct mpc5xxx_gpt_0_7 {
  810. struct mpc5xxx_gpt gpt0;
  811. struct mpc5xxx_gpt gpt1;
  812. struct mpc5xxx_gpt gpt2;
  813. struct mpc5xxx_gpt gpt3;
  814. struct mpc5xxx_gpt gpt4;
  815. struct mpc5xxx_gpt gpt5;
  816. struct mpc5xxx_gpt gpt6;
  817. struct mpc5xxx_gpt gpt7;
  818. };
  819. struct mscan_buffer {
  820. volatile u8 idr[0x8]; /* 0x00 */
  821. volatile u8 dsr[0x10]; /* 0x08 */
  822. volatile u8 dlr; /* 0x18 */
  823. volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */
  824. volatile u16 rsrv1; /* 0x1A */
  825. volatile u8 tsrh; /* 0x1C */
  826. volatile u8 tsrl; /* 0x1D */
  827. volatile u16 rsrv2; /* 0x1E */
  828. };
  829. struct mpc5xxx_mscan {
  830. volatile u8 canctl0; /* MSCAN + 0x00 */
  831. volatile u8 canctl1; /* MSCAN + 0x01 */
  832. volatile u16 rsrv1; /* MSCAN + 0x02 */
  833. volatile u8 canbtr0; /* MSCAN + 0x04 */
  834. volatile u8 canbtr1; /* MSCAN + 0x05 */
  835. volatile u16 rsrv2; /* MSCAN + 0x06 */
  836. volatile u8 canrflg; /* MSCAN + 0x08 */
  837. volatile u8 canrier; /* MSCAN + 0x09 */
  838. volatile u16 rsrv3; /* MSCAN + 0x0A */
  839. volatile u8 cantflg; /* MSCAN + 0x0C */
  840. volatile u8 cantier; /* MSCAN + 0x0D */
  841. volatile u16 rsrv4; /* MSCAN + 0x0E */
  842. volatile u8 cantarq; /* MSCAN + 0x10 */
  843. volatile u8 cantaak; /* MSCAN + 0x11 */
  844. volatile u16 rsrv5; /* MSCAN + 0x12 */
  845. volatile u8 cantbsel; /* MSCAN + 0x14 */
  846. volatile u8 canidac; /* MSCAN + 0x15 */
  847. volatile u16 rsrv6[3]; /* MSCAN + 0x16 */
  848. volatile u8 canrxerr; /* MSCAN + 0x1C */
  849. volatile u8 cantxerr; /* MSCAN + 0x1D */
  850. volatile u16 rsrv7; /* MSCAN + 0x1E */
  851. volatile u8 canidar0; /* MSCAN + 0x20 */
  852. volatile u8 canidar1; /* MSCAN + 0x21 */
  853. volatile u16 rsrv8; /* MSCAN + 0x22 */
  854. volatile u8 canidar2; /* MSCAN + 0x24 */
  855. volatile u8 canidar3; /* MSCAN + 0x25 */
  856. volatile u16 rsrv9; /* MSCAN + 0x26 */
  857. volatile u8 canidmr0; /* MSCAN + 0x28 */
  858. volatile u8 canidmr1; /* MSCAN + 0x29 */
  859. volatile u16 rsrv10; /* MSCAN + 0x2A */
  860. volatile u8 canidmr2; /* MSCAN + 0x2C */
  861. volatile u8 canidmr3; /* MSCAN + 0x2D */
  862. volatile u16 rsrv11; /* MSCAN + 0x2E */
  863. volatile u8 canidar4; /* MSCAN + 0x30 */
  864. volatile u8 canidar5; /* MSCAN + 0x31 */
  865. volatile u16 rsrv12; /* MSCAN + 0x32 */
  866. volatile u8 canidar6; /* MSCAN + 0x34 */
  867. volatile u8 canidar7; /* MSCAN + 0x35 */
  868. volatile u16 rsrv13; /* MSCAN + 0x36 */
  869. volatile u8 canidmr4; /* MSCAN + 0x38 */
  870. volatile u8 canidmr5; /* MSCAN + 0x39 */
  871. volatile u16 rsrv14; /* MSCAN + 0x3A */
  872. volatile u8 canidmr6; /* MSCAN + 0x3C */
  873. volatile u8 canidmr7; /* MSCAN + 0x3D */
  874. volatile u16 rsrv15; /* MSCAN + 0x3E */
  875. struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */
  876. struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */
  877. };
  878. struct mpc5xxx_xlb {
  879. volatile u8 reserved[0x40]; /* XLB + 0x00 */
  880. volatile u32 config; /* XLB + 0x40 */
  881. volatile u32 version; /* XLB + 0x44 */
  882. volatile u32 status; /* XLB + 0x48 */
  883. volatile u32 int_enable; /* XLB + 0x4c */
  884. volatile u32 addr_capture; /* XLB + 0x50 */
  885. volatile u32 bus_sig_capture; /* XLB + 0x54 */
  886. volatile u32 addr_timeout; /* XLB + 0x58 */
  887. volatile u32 data_timeout; /* XLB + 0x5c */
  888. volatile u32 bus_act_timeout; /* XLB + 0x60 */
  889. volatile u32 master_pri_enable; /* XLB + 0x64 */
  890. volatile u32 master_priority; /* XLB + 0x68 */
  891. volatile u32 base_address; /* XLB + 0x6c */
  892. volatile u32 snoop_window; /* XLB + 0x70 */
  893. };
  894. /* function prototypes */
  895. void loadtask(int basetask, int tasks);
  896. #endif /* __ASSEMBLY__ */
  897. #endif /* __ASMPPC_MPC5XXX_H */