mpc5xx.h 8.3 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * File: mpc5xx.h
  25. *
  26. * Discription: mpc5xx specific definitions
  27. *
  28. */
  29. #ifndef __MPC5XX_H__
  30. #define __MPC5XX_H__
  31. /*-----------------------------------------------------------------------
  32. * Exception offsets (PowerPC standard)
  33. */
  34. #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  35. #define _START_OFFSET EXC_OFF_SYS_RESET
  36. /*-----------------------------------------------------------------------
  37. * ISB bit in IMMR to set internal memory map
  38. */
  39. #define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1)
  40. /*-----------------------------------------------------------------------
  41. * SYPCR - System Protection Control Register
  42. */
  43. #define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
  44. #define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
  45. #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
  46. #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
  47. #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
  48. #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
  49. #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
  50. /*-----------------------------------------------------------------------
  51. * SIUMCR - SIU Module Configuration Register
  52. */
  53. #define SIUMCR_EARB 0x80000000 /* External Arbitration */
  54. #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
  55. #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
  56. #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
  57. #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
  58. #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
  59. #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
  60. #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
  61. #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
  62. #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
  63. #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
  64. #define SIUMCR_DBGC01 0x00200000 /* - " - */
  65. #define SIUMCR_DBGC10 0x00400000 /* - " - */
  66. #define SIUMCR_DBGC11 0x00600000 /* - " - */
  67. #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
  68. #define SIUMCR_DBPC01 0x00080000 /* - " - */
  69. #define SIUMCR_DBPC10 0x00100000 /* - " - */
  70. #define SIUMCR_DBPC11 0x00180000 /* - " - */
  71. #define SIUMCR_GPC00 0x00000000 /* General Pins Config */
  72. #define SIUMCR_GPC01 0x00020000 /* General Pins Config */
  73. #define SIUMCR_GPC10 0x00040000 /* General Pins Config */
  74. #define SIUMCR_GPC11 0x00060000 /* General Pins Config */
  75. #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
  76. #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
  77. #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
  78. #define SIUMCR_SC10 0x00004000 /* Single adress show */
  79. #define SIUMCR_SC11 0x00006000 /* Single adress */
  80. #define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
  81. #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
  82. #define SIUMCR_MLRC01 0x00000400 /* - " - */
  83. #define SIUMCR_MLRC10 0x00000800 /* - " - */
  84. #define SIUMCR_MLRC11 0x00000c00 /* - " - */
  85. #define SIUMCR_MTSC 0x00000100 /* Memory transfer */
  86. /*-----------------------------------------------------------------------
  87. * TBSCR - Time Base Status and Control Register
  88. */
  89. #define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
  90. #define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
  91. #define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
  92. /*-----------------------------------------------------------------------
  93. * PISCR - Periodic Interrupt Status and Control Register
  94. */
  95. #define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
  96. #define PISCR_PS 0x0080 /* Periodic Interrupt Status */
  97. /*-----------------------------------------------------------------------
  98. * PLPRCR - PLL, Low-Power, and Reset Control Register
  99. */
  100. #define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
  101. #define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
  102. #define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
  103. #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
  104. #define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
  105. #define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
  106. #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
  107. #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
  108. #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
  109. #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
  110. /*-----------------------------------------------------------------------
  111. * SCCR - System Clock and reset Control Register
  112. */
  113. #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
  114. #define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
  115. #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
  116. #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
  117. #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
  118. #define SCCR_EBDF11 0x00060000 /* reserved */
  119. #define SCCR_TBS 0x02000000 /* Time Base Source */
  120. #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
  121. #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
  122. #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
  123. #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
  124. #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
  125. /*-----------------------------------------------------------------------
  126. * MC - Memory Controller
  127. */
  128. #define BR_V 0x00000001 /* Bank valid */
  129. #define BR_BI 0x00000002 /* Burst inhibit */
  130. #define BR_PS_8 0x00000400 /* 8 bit port size */
  131. #define BR_PS_16 0x00000800 /* 16 bit port size */
  132. #define BR_PS_32 0x00000000 /* 32 bit port size */
  133. #define BR_LBDIR 0x00000008 /* Late burst data in progess */
  134. #define BR_SETA 0x00000004 /* External Data Acknowledge */
  135. #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
  136. #define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
  137. #define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
  138. #define OR_TRLX 0x00000001 /* Timing relaxed */
  139. #define OR_BSCY 0x00000060 /* Burst beats length in clocks */
  140. #define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
  141. #define OR_CSNT 0x00000800 /* Chip-select negotation time */
  142. #define OR_ETHR 0x00000100 /* Extended hold time on read */
  143. #define OR_ADDR_MK_FF 0xFF000000
  144. #define OR_ADDR_MK_FFFF 0xFFFF0000
  145. /*-----------------------------------------------------------------------
  146. * UMCR - UIMB Module Configuration Register
  147. */
  148. #define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
  149. #define UMCR_HSPEED 0x10000000 /* Half speed */
  150. /*-----------------------------------------------------------------------
  151. * ICTRL - I-Bus Support Control Register
  152. */
  153. #define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */
  154. #define NR_IRQS 0 /* Place this later in a separate file */
  155. /*-----------------------------------------------------------------------
  156. * SCI - Serial communication interface
  157. */
  158. #define SCI_TDRE 0x0100 /* Transmit data register empty */
  159. #define SCI_TE 0x0008 /* Transmitter enabled */
  160. #define SCI_RE 0x0004 /* Receiver enabled */
  161. #define SCI_RDRF 0x0040 /* Receive data register full */
  162. #define SCI_PE 0x0400 /* Parity enable */
  163. #define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
  164. #define SCI_SCXDR_MK 0x00ff /* Data register mask */
  165. #define SCI_M_11 0x0200 /* Frame size is 11 bit */
  166. #define SCI_M_10 0x0000 /* Frame size is 10 bit */
  167. #define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
  168. #define SCI_PORT_2 ((int)2)
  169. #endif /* __MPC5XX_H__ */