mpc106.h 4.8 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef _MPC106_PCI_H
  24. #define _MPC106_PCI_H
  25. /*
  26. * Defines for the MPC106 PCI Config address and data registers followed by
  27. * defines for the standard PCI device configuration header.
  28. */
  29. #define PCIDEVID_MPC106 0x0
  30. /*
  31. * MPC106 Registers
  32. */
  33. #define MPC106_REG 0x80000000
  34. #ifdef CONFIG_SYS_ADDRESS_MAP_A
  35. #define MPC106_REG_ADDR 0x80000cf8
  36. #define MPC106_REG_DATA 0x80000cfc
  37. #define MPC106_ISA_IO_PHYS 0x80000000
  38. #define MPC106_ISA_IO_BUS 0x00000000
  39. #define MPC106_ISA_IO_SIZE 0x00800000
  40. #define MPC106_PCI_IO_PHYS 0x81000000
  41. #define MPC106_PCI_IO_BUS 0x01000000
  42. #define MPC106_PCI_IO_SIZE 0x3e800000
  43. #define MPC106_PCI_MEM_PHYS 0xc0000000
  44. #define MPC106_PCI_MEM_BUS 0x00000000
  45. #define MPC106_PCI_MEM_SIZE 0x3f000000
  46. #define MPC106_PCI_MEMORY_PHYS 0x00000000
  47. #define MPC106_PCI_MEMORY_BUS 0x80000000
  48. #define MPC106_PCI_MEMORY_SIZE 0x80000000
  49. #else
  50. #define MPC106_REG_ADDR 0xfec00cf8
  51. #define MPC106_REG_DATA 0xfee00cfc
  52. #define MPC106_ISA_MEM_PHYS 0xfd000000
  53. #define MPC106_ISA_MEM_BUS 0x00000000
  54. #define MPC106_ISA_MEM_SIZE 0x01000000
  55. #define MPC106_ISA_IO_PHYS 0xfe000000
  56. #define MPC106_ISA_IO_BUS 0x00000000
  57. #define MPC106_ISA_IO_SIZE 0x00800000
  58. #define MPC106_PCI_IO_PHYS 0xfe800000
  59. #define MPC106_PCI_IO_BUS 0x00800000
  60. #define MPC106_PCI_IO_SIZE 0x00400000
  61. #define MPC106_PCI_MEM_PHYS 0x80000000
  62. #define MPC106_PCI_MEM_BUS 0x80000000
  63. #define MPC106_PCI_MEM_SIZE 0x7d000000
  64. #define MPC106_PCI_MEMORY_PHYS 0x00000000
  65. #define MPC106_PCI_MEMORY_BUS 0x00000000
  66. #define MPC106_PCI_MEMORY_SIZE 0x40000000
  67. #endif
  68. #define CMD_SERR 0x0100
  69. #define PCI_CMD_MASTER 0x0004
  70. #define PCI_CMD_MEMEN 0x0002
  71. #define PCI_CMD_IOEN 0x0001
  72. #define PCI_STAT_NO_RSV_BITS 0xffff
  73. #define PCI_BUSNUM 0x40
  74. #define PCI_SUBBUSNUM 0x41
  75. #define PCI_DISCOUNT 0x42
  76. #define PCI_PICR1 0xA8
  77. #define PICR1_CF_CBA(value) ((value & 0xff) << 24)
  78. #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
  79. #define PICR1_PROC_TYPE_603 0x40000
  80. #define PICR1_PROC_TYPE_604 0x60000
  81. #define PICR1_MCP_EN 0x800
  82. #define PICR1_CF_DPARK 0x200
  83. #define PICR1_CF_LOOP_SNOOP 0x10
  84. #define PICR1_CF_L2_COPY_BACK 0x2
  85. #define PICR1_CF_L2_CACHE_MASK 0x3
  86. #define PICR1_CF_APARK 0x8
  87. #define PICR1_ADDRESS_MAP 0x10000
  88. #define PICR1_XIO_MODE 0x80000
  89. #define PICR1_CF_CACHE_1G 0x200000
  90. #define PCI_PICR2 0xAC
  91. #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18)
  92. #define PICR2_CF_FLUSH_L2 0x10000000
  93. #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
  94. #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2)
  95. #define PICR2_CF_INV_MODE 0x00001000
  96. #define PICR2_CF_MOD_HIGH 0x00020000
  97. #define PICR2_CF_HIT_HIGH 0x00010000
  98. #define PICR2_L2_SIZE_256K 0x00000000
  99. #define PICR2_L2_SIZE_512K 0x00000010
  100. #define PICR2_L2_SIZE_1MB 0x00000020
  101. #define PICR2_L2_EN 0x40000000
  102. #define PICR2_L2_UPDATE_EN 0x80000000
  103. #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000
  104. #define PICR2_CF_FAST_CASTOUT 0x00000080
  105. #define PICR2_CF_WDATA 0x00000001
  106. #define PICR2_CF_DATA_RAM_PBURST 0x00400000
  107. /*
  108. * Memory controller
  109. */
  110. #define MPC106_MCCR1 0xF0
  111. #define MCCR1_TYPE_EDO 0x00020000
  112. #define MCCR1_BK0_9BITS 0x0
  113. #define MCCR1_BK0_10BITS 0x1
  114. #define MCCR1_BK0_11BITS 0x2
  115. #define MCCR1_BK0_12BITS 0x3
  116. #define MCCR1_BK1_9BITS 0x0
  117. #define MCCR1_BK1_10BITS 0x4
  118. #define MCCR1_BK1_11BITS 0x8
  119. #define MCCR1_BK1_12BITS 0xC
  120. #define MCCR1_BK2_9BITS 0x00
  121. #define MCCR1_BK2_10BITS 0x10
  122. #define MCCR1_BK2_11BITS 0x20
  123. #define MCCR1_BK2_12BITS 0x30
  124. #define MCCR1_BK3_9BITS 0x00
  125. #define MCCR1_BK3_10BITS 0x40
  126. #define MCCR1_BK3_11BITS 0x80
  127. #define MCCR1_BK3_12BITS 0xC0
  128. #define MCCR1_MEMGO 0x00080000
  129. #define MPC106_MCCR2 0xF4
  130. #define MPC106_MCCR3 0xF8
  131. #define MPC106_MCCR4 0xFC
  132. #define MPC106_MSAR1 0x80
  133. #define MPC106_EMSAR1 0x88
  134. #define MPC106_EMSAR2 0x8C
  135. #define MPC106_MEAR1 0x90
  136. #define MPC106_EMEAR1 0x98
  137. #define MPC106_EMEAR2 0x9C
  138. #define MPC106_MBER 0xA0
  139. #define MBER_BANK0 0x1
  140. #define MBER_BANK1 0x2
  141. #define MBER_BANK2 0x4
  142. #define MBER_BANK3 0x8
  143. #endif