lxt971a.h 5.9 KB

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  1. /***********************************************************************
  2. *
  3. * Copyright (C) 2004 by FS Forth-Systeme GmbH.
  4. * All rights reserved.
  5. *
  6. * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
  7. * @Author: Markus Pietrek
  8. * @References: [1] NS9750 Hardware Reference, December 2003
  9. * [2] Intel LXT971 Datasheet #249414 Rev. 02
  10. * [3] NS7520 Linux Ethernet Driver
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. ***********************************************************************/
  28. #ifndef __LXT971A_H__
  29. #define __LXT971A_H__
  30. /* PHY definitions (LXT971A) [2] */
  31. #define PHY_LXT971_PORT_CFG (0x10)
  32. #define PHY_LXT971_STAT2 (0x11)
  33. #define PHY_LXT971_INT_ENABLE (0x12)
  34. #define PHY_LXT971_INT_STATUS (0x13)
  35. #define PHY_LXT971_LED_CFG (0x14)
  36. #define PHY_LXT971_DIG_CFG (0x1A)
  37. #define PHY_LXT971_TX_CTRL (0x1E)
  38. /* PORT_CFG Port Configuration Register Bit Fields */
  39. #define PHY_LXT971_PORT_CFG_RES1 (0x8000)
  40. #define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
  41. #define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
  42. #define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
  43. #define PHY_LXT971_PORT_CFG_RES2 (0x0800)
  44. #define PHY_LXT971_PORT_CFG_JABBER (0x0400)
  45. #define PHY_LXT971_PORT_CFG_SQE (0x0200)
  46. #define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
  47. #define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
  48. #define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
  49. #define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
  50. #define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
  51. #define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
  52. #define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
  53. #define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
  54. #define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
  55. #define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
  56. #define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
  57. /* STAT2 Status Register #2 Bit Fields */
  58. #define PHY_LXT971_STAT2_RES1 (0x8000)
  59. #define PHY_LXT971_STAT2_100BTX (0x4000)
  60. #define PHY_LXT971_STAT2_TX_STATUS (0x2000)
  61. #define PHY_LXT971_STAT2_RX_STATUS (0x1000)
  62. #define PHY_LXT971_STAT2_COL_STATUS (0x0800)
  63. #define PHY_LXT971_STAT2_LINK (0x0400)
  64. #define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
  65. #define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
  66. #define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
  67. #define PHY_LXT971_STAT2_RES2 (0x0040)
  68. #define PHY_LXT971_STAT2_POLARITY (0x0020)
  69. #define PHY_LXT971_STAT2_PAUSE (0x0010)
  70. #define PHY_LXT971_STAT2_ERROR (0x0008)
  71. #define PHY_LXT971_STAT2_RES3 (0x0007)
  72. /* INT_ENABLE Interrupt Enable Register Bit Fields */
  73. #define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
  74. #define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
  75. #define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
  76. #define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
  77. #define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
  78. #define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
  79. #define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
  80. #define PHY_LXT971_INT_ENABLE_TINT (0x0001)
  81. /* INT_STATUS Interrupt Status Register Bit Fields */
  82. #define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
  83. #define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
  84. #define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
  85. #define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
  86. #define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
  87. #define PHY_LXT971_INT_STATUS_RES2 (0x0008)
  88. #define PHY_LXT971_INT_STATUS_MDINT (0x0004)
  89. #define PHY_LXT971_INT_STATUS_RES3 (0x0003)
  90. /* LED_CFG Interrupt LED Configuration Register Bit Fields */
  91. #define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
  92. #define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
  93. #define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
  94. #define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
  95. #define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
  96. #define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
  97. #define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
  98. #define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
  99. #define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
  100. #define PHY_LXT971_LED_CFG_RES1 (0x0001)
  101. /* only one of these values must be shifted for each SHIFT_LED? */
  102. #define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
  103. #define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
  104. #define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
  105. #define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
  106. #define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
  107. #define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
  108. #define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
  109. #define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
  110. #define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
  111. #define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
  112. #define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
  113. #define PHY_LXT971_LED_CFG_LINK (0x0004)
  114. #define PHY_LXT971_LED_CFG_COLLISION (0x0003)
  115. #define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
  116. #define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
  117. #define PHY_LXT971_LED_CFG_SPEED (0x0000)
  118. /* DIG_CFG Digitial Configuration Register Bit Fields */
  119. #define PHY_LXT971_DIG_CFG_RES1 (0xF000)
  120. #define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
  121. #define PHY_LXT971_DIG_CFG_RES2 (0x0400)
  122. #define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
  123. #define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
  124. #define PHY_LXT971_MDIO_MAX_CLK (8000000)
  125. #define PHY_MDIO_MAX_CLK (2500000)
  126. /* TX_CTRL Transmit Control Register Bit Fields
  127. documentation is buggy for this register, therefore setting not included */
  128. typedef enum
  129. {
  130. PHY_NONE = 0x0000, /* no PHY detected yet */
  131. PHY_LXT971A = 0x0013
  132. } PhyType;
  133. #endif /* __LXT971A_H__ */