lh7a40x.h 8.0 KB

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  1. /*
  2. * See file CREDITS for list of people who contributed to this
  3. * project.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. /*
  21. * lh7a40x SoC series common interface
  22. */
  23. #ifndef __LH7A40X_H__
  24. #define __LH7A40X_H__
  25. /* (SMC) Static Memory Controller (usersguide 4.2.1) */
  26. typedef struct {
  27. volatile u32 attib;
  28. volatile u32 com;
  29. volatile u32 io;
  30. volatile u32 rsvd1;
  31. } /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
  32. typedef struct {
  33. volatile u32 bcr[8];
  34. lh7a40x_pccard_t pccard[2];
  35. volatile u32 pcmciacon;
  36. } /*__attribute__((__packed__))*/ lh7a40x_smc_t;
  37. #define LH7A40X_SMC_BASE (0x80002000)
  38. #define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
  39. /* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
  40. typedef struct {
  41. volatile u32 rsvd1;
  42. volatile u32 gblcnfg;
  43. volatile u32 rfshtmr;
  44. volatile u32 bootstat;
  45. volatile u32 sdcsc[4];
  46. } /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
  47. #define LH7A40X_SDMC_BASE (0x80002400)
  48. #define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
  49. /* (CSC) Clock and State Controller (userguide 6.2.1) */
  50. typedef struct {
  51. volatile u32 pwrsr;
  52. volatile u32 pwrcnt;
  53. volatile u32 halt;
  54. volatile u32 stby;
  55. volatile u32 bleoi;
  56. volatile u32 mceoi;
  57. volatile u32 teoi;
  58. volatile u32 stfclr;
  59. volatile u32 clkset;
  60. volatile u32 scrreg[2];
  61. volatile u32 rsvd1;
  62. volatile u32 usbreset;
  63. } /*__attribute__((__packed__))*/ lh7a40x_csc_t;
  64. #define LH7A40X_STPWR_BASE (0x80000400)
  65. #define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
  66. #define CLKSET_SMCROM (0x01000000)
  67. #define CLKSET_PS (0x000C0000)
  68. #define CLKSET_PS_0 (0x00000000)
  69. #define CLKSET_PS_1 (0x00040000)
  70. #define CLKSET_PS_2 (0x00080000)
  71. #define CLKSET_PS_3 (0x000C0000)
  72. #define CLKSET_PCLKDIV (0x00030000)
  73. #define CLKSET_PCLKDIV_2 (0x00000000)
  74. #define CLKSET_PCLKDIV_4 (0x00010000)
  75. #define CLKSET_PCLKDIV_8 (0x00020000)
  76. #define CLKSET_MAINDIV2 (0x0000f800)
  77. #define CLKSET_MAINDIV1 (0x00000780)
  78. #define CLKSET_PREDIV (0x0000007C)
  79. #define CLKSET_HCLKDIV (0x00000003)
  80. /* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
  81. typedef struct {
  82. volatile u32 maxcnt;
  83. volatile u32 base;
  84. volatile u32 current;
  85. volatile u32 rsvd1;
  86. } lh7a40x_dmabuf_t;
  87. typedef struct {
  88. volatile u32 control;
  89. volatile u32 interrupt;
  90. volatile u32 rsvd1;
  91. volatile u32 status;
  92. volatile u32 rsvd2;
  93. volatile u32 remain;
  94. volatile u32 rsvd3;
  95. volatile u32 rsvd4;
  96. lh7a40x_dmabuf_t buf[2];
  97. } /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
  98. /* (WDT) Watchdog Timer (userguide 11.2.1) */
  99. typedef struct {
  100. volatile u32 ctl;
  101. volatile u32 rst;
  102. volatile u32 status;
  103. volatile u32 count[4];
  104. } /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
  105. #define LH7A40X_WDT_BASE (0x80001400)
  106. #define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
  107. /* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
  108. typedef struct {
  109. volatile u32 rtcdr;
  110. volatile u32 rtclr;
  111. volatile u32 rtcmr;
  112. volatile u32 unk1;
  113. volatile u32 rtcstat_eoi;
  114. volatile u32 rtccr;
  115. volatile u32 rsvd1[58];
  116. } /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
  117. #define LH7A40X_RTC_BASE (0x80000D00)
  118. #define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
  119. /* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
  120. typedef struct {
  121. volatile u32 load;
  122. volatile u32 value;
  123. volatile u32 control;
  124. volatile u32 tceoi;
  125. } /*__attribute__((__packed__))*/ lh7a40x_timer_t;
  126. typedef struct {
  127. lh7a40x_timer_t timer1;
  128. volatile u32 rsvd1[4];
  129. lh7a40x_timer_t timer2;
  130. volatile u32 unk1[4];
  131. volatile u32 bzcon;
  132. volatile u32 unk2[15];
  133. lh7a40x_timer_t timer3;
  134. /*volatile u32 rsvd2;*/
  135. } /*__attribute__((__packed__))*/ lh7a40x_timers_t;
  136. #define LH7A40X_TIMERS_BASE (0x80000C00)
  137. #define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
  138. #define TIMER_EN (0x00000080)
  139. #define TIMER_PER (0x00000040)
  140. #define TIMER_FREE (0x00000000)
  141. #define TIMER_CLK508K (0x00000008)
  142. #define TIMER_CLK2K (0x00000000)
  143. /* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
  144. typedef struct {
  145. volatile u32 cr0;
  146. volatile u32 cr1;
  147. volatile u32 irr_roeoi;
  148. volatile u32 dr;
  149. volatile u32 cpr;
  150. volatile u32 sr;
  151. /*volatile u32 rsvd1[58];*/
  152. } /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
  153. #define LH7A40X_SSP_BASE (0x80000B00)
  154. #define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
  155. /* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
  156. typedef struct {
  157. volatile u32 data;
  158. volatile u32 fcon;
  159. volatile u32 brcon;
  160. volatile u32 con;
  161. volatile u32 status;
  162. volatile u32 rawisr;
  163. volatile u32 inten;
  164. volatile u32 isr;
  165. volatile u32 rsvd1[56];
  166. } /*__attribute__((__packed__))*/ lh7a40x_uart_t;
  167. #define LH7A40X_UART_BASE (0x80000600)
  168. #define LH7A40X_UART_PTR(n) \
  169. ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
  170. #define UART_BE (0x00000800) /* the rx error bits */
  171. #define UART_OE (0x00000400)
  172. #define UART_PE (0x00000200)
  173. #define UART_FE (0x00000100)
  174. #define UART_WLEN (0x00000060) /* fcon bits */
  175. #define UART_WLEN_8 (0x00000060)
  176. #define UART_WLEN_7 (0x00000040)
  177. #define UART_WLEN_6 (0x00000020)
  178. #define UART_WLEN_5 (0x00000000)
  179. #define UART_FEN (0x00000010)
  180. #define UART_STP2 (0x00000008)
  181. #define UART_STP2_2 (0x00000008)
  182. #define UART_STP2_1 (0x00000000)
  183. #define UART_EPS (0x00000004)
  184. #define UART_EPS_EVEN (0x00000004)
  185. #define UART_EPS_ODD (0x00000000)
  186. #define UART_PEN (0x00000002)
  187. #define UART_BRK (0x00000001)
  188. #define UART_BAUDDIV (0x0000ffff) /* brcon bits */
  189. #define UART_SIRBD (0x00000080) /* con bits */
  190. #define UART_LBE (0x00000040)
  191. #define UART_MXP (0x00000020)
  192. #define UART_TXP (0x00000010)
  193. #define UART_RXP (0x00000008)
  194. #define UART_SIRLP (0x00000004)
  195. #define UART_SIRD (0x00000002)
  196. #define UART_EN (0x00000001)
  197. #define UART_TXFE (0x00000080) /* status bits */
  198. #define UART_RXFF (0x00000040)
  199. #define UART_TXFF (0x00000020)
  200. #define UART_RXFE (0x00000010)
  201. #define UART_BUSY (0x00000008)
  202. #define UART_DCD (0x00000004)
  203. #define UART_DSR (0x00000002)
  204. #define UART_CTS (0x00000001)
  205. #define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */
  206. #define UART_RTI (0x00000008) /* generic interrupt bits */
  207. #define UART_MI (0x00000004)
  208. #define UART_TI (0x00000002)
  209. #define UART_RI (0x00000001)
  210. /* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
  211. typedef struct {
  212. volatile u32 pad;
  213. volatile u32 pbd;
  214. volatile u32 pcd;
  215. volatile u32 pdd;
  216. volatile u32 padd;
  217. volatile u32 pbdd;
  218. volatile u32 pcdd;
  219. volatile u32 pddd;
  220. volatile u32 ped;
  221. volatile u32 pedd;
  222. volatile u32 kbdctl;
  223. volatile u32 pinmux;
  224. volatile u32 pfd;
  225. volatile u32 pfdd;
  226. volatile u32 pgd;
  227. volatile u32 pgdd;
  228. volatile u32 phd;
  229. volatile u32 phdd;
  230. volatile u32 rsvd1;
  231. volatile u32 inttype1;
  232. volatile u32 inttype2;
  233. volatile u32 gpiofeoi;
  234. volatile u32 gpiointen;
  235. volatile u32 intstatus;
  236. volatile u32 rawintstatus;
  237. volatile u32 gpiodb;
  238. volatile u32 papd;
  239. volatile u32 pbpd;
  240. volatile u32 pcpd;
  241. volatile u32 pdpd;
  242. volatile u32 pepd;
  243. volatile u32 pfpd;
  244. volatile u32 pgpd;
  245. volatile u32 phpd;
  246. } /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
  247. #define LH7A40X_GPIOINT_BASE (0x80000E00)
  248. #define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
  249. /* Embedded SRAM */
  250. #define CONFIG_SYS_SRAM_BASE (0xB0000000)
  251. #define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */
  252. #endif /* __LH7A40X_H__ */