clps7111.h 8.7 KB

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  1. /*
  2. * linux/include/asm-arm/hardware/clps7111.h
  3. *
  4. * This file contains the hardware definitions of the CLPS7111 internal
  5. * registers.
  6. *
  7. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #ifndef __ASM_HARDWARE_CLPS7111_H
  24. #define __ASM_HARDWARE_CLPS7111_H
  25. #define CLPS7111_PHYS_BASE (0x80000000)
  26. #ifndef __ASSEMBLY__
  27. #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
  28. #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
  29. #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
  30. #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
  31. #endif
  32. #define PADR (0x0000)
  33. #define PBDR (0x0001)
  34. #define PDDR (0x0003)
  35. #define PADDR (0x0040)
  36. #define PBDDR (0x0041)
  37. #define PDDDR (0x0043)
  38. #define PEDR (0x0080)
  39. #define PEDDR (0x00c0)
  40. #define SYSCON1 (0x0100)
  41. #define SYSFLG1 (0x0140)
  42. #define MEMCFG1 (0x0180)
  43. #define MEMCFG2 (0x01c0)
  44. #define DRFPR (0x0200)
  45. #define INTSR1 (0x0240)
  46. #define INTMR1 (0x0280)
  47. #define LCDCON (0x02c0)
  48. #define TC1D (0x0300)
  49. #define TC2D (0x0340)
  50. #define RTCDR (0x0380)
  51. #define RTCMR (0x03c0)
  52. #define PMPCON (0x0400)
  53. #define CODR (0x0440)
  54. #define UARTDR1 (0x0480)
  55. #define UBRLCR1 (0x04c0)
  56. #define SYNCIO (0x0500)
  57. #define PALLSW (0x0540)
  58. #define PALMSW (0x0580)
  59. #define STFCLR (0x05c0)
  60. #define BLEOI (0x0600)
  61. #define MCEOI (0x0640)
  62. #define TEOI (0x0680)
  63. #define TC1EOI (0x06c0)
  64. #define TC2EOI (0x0700)
  65. #define RTCEOI (0x0740)
  66. #define UMSEOI (0x0780)
  67. #define COEOI (0x07c0)
  68. #define HALT (0x0800)
  69. #define STDBY (0x0840)
  70. #define FBADDR (0x1000)
  71. #define SYSCON2 (0x1100)
  72. #define SYSFLG2 (0x1140)
  73. #define INTSR2 (0x1240)
  74. #define INTMR2 (0x1280)
  75. #define UARTDR2 (0x1480)
  76. #define UBRLCR2 (0x14c0)
  77. #define SS2DR (0x1500)
  78. #define SRXEOF (0x1600)
  79. #define SS2POP (0x16c0)
  80. #define KBDEOI (0x1700)
  81. /* common bits: SYSCON1 / SYSCON2 */
  82. #define SYSCON_UARTEN (1 << 8)
  83. #define SYSCON1_KBDSCAN(x) ((x) & 15)
  84. #define SYSCON1_KBDSCANMASK (15)
  85. #define SYSCON1_TC1M (1 << 4)
  86. #define SYSCON1_TC1S (1 << 5)
  87. #define SYSCON1_TC2M (1 << 6)
  88. #define SYSCON1_TC2S (1 << 7)
  89. #define SYSCON1_UART1EN SYSCON_UARTEN
  90. #define SYSCON1_BZTOG (1 << 9)
  91. #define SYSCON1_BZMOD (1 << 10)
  92. #define SYSCON1_DBGEN (1 << 11)
  93. #define SYSCON1_LCDEN (1 << 12)
  94. #define SYSCON1_CDENTX (1 << 13)
  95. #define SYSCON1_CDENRX (1 << 14)
  96. #define SYSCON1_SIREN (1 << 15)
  97. #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
  98. #define SYSCON1_ADCKSEL_MASK (3 << 16)
  99. #define SYSCON1_EXCKEN (1 << 18)
  100. #define SYSCON1_WAKEDIS (1 << 19)
  101. #define SYSCON1_IRTXM (1 << 20)
  102. /* common bits: SYSFLG1 / SYSFLG2 */
  103. #define SYSFLG_UBUSY (1 << 11)
  104. #define SYSFLG_URXFE (1 << 22)
  105. #define SYSFLG_UTXFF (1 << 23)
  106. #define SYSFLG1_MCDR (1 << 0)
  107. #define SYSFLG1_DCDET (1 << 1)
  108. #define SYSFLG1_WUDR (1 << 2)
  109. #define SYSFLG1_WUON (1 << 3)
  110. #define SYSFLG1_CTS (1 << 8)
  111. #define SYSFLG1_DSR (1 << 9)
  112. #define SYSFLG1_DCD (1 << 10)
  113. #define SYSFLG1_UBUSY SYSFLG_UBUSY
  114. #define SYSFLG1_NBFLG (1 << 12)
  115. #define SYSFLG1_RSTFLG (1 << 13)
  116. #define SYSFLG1_PFFLG (1 << 14)
  117. #define SYSFLG1_CLDFLG (1 << 15)
  118. #define SYSFLG1_URXFE SYSFLG_URXFE
  119. #define SYSFLG1_UTXFF SYSFLG_UTXFF
  120. #define SYSFLG1_CRXFE (1 << 24)
  121. #define SYSFLG1_CTXFF (1 << 25)
  122. #define SYSFLG1_SSIBUSY (1 << 26)
  123. #define SYSFLG1_ID (1 << 29)
  124. #define SYSFLG2_SSRXOF (1 << 0)
  125. #define SYSFLG2_RESVAL (1 << 1)
  126. #define SYSFLG2_RESFRM (1 << 2)
  127. #define SYSFLG2_SS2RXFE (1 << 3)
  128. #define SYSFLG2_SS2TXFF (1 << 4)
  129. #define SYSFLG2_SS2TXUF (1 << 5)
  130. #define SYSFLG2_CKMODE (1 << 6)
  131. #define SYSFLG2_UBUSY SYSFLG_UBUSY
  132. #define SYSFLG2_URXFE SYSFLG_URXFE
  133. #define SYSFLG2_UTXFF SYSFLG_UTXFF
  134. #define LCDCON_GSEN (1 << 30)
  135. #define LCDCON_GSMD (1 << 31)
  136. #define SYSCON2_SERSEL (1 << 0)
  137. #define SYSCON2_KBD6 (1 << 1)
  138. #define SYSCON2_DRAMZ (1 << 2)
  139. #define SYSCON2_KBWEN (1 << 3)
  140. #define SYSCON2_SS2TXEN (1 << 4)
  141. #define SYSCON2_PCCARD1 (1 << 5)
  142. #define SYSCON2_PCCARD2 (1 << 6)
  143. #define SYSCON2_SS2RXEN (1 << 7)
  144. #define SYSCON2_UART2EN SYSCON_UARTEN
  145. #define SYSCON2_SS2MAEN (1 << 9)
  146. #define SYSCON2_OSTB (1 << 12)
  147. #define SYSCON2_CLKENSL (1 << 13)
  148. #define SYSCON2_BUZFREQ (1 << 14)
  149. /* common bits: UARTDR1 / UARTDR2 */
  150. #define UARTDR_FRMERR (1 << 8)
  151. #define UARTDR_PARERR (1 << 9)
  152. #define UARTDR_OVERR (1 << 10)
  153. /* common bits: UBRLCR1 / UBRLCR2 */
  154. #define UBRLCR_BAUD_MASK ((1 << 12) - 1)
  155. #define UBRLCR_BREAK (1 << 12)
  156. #define UBRLCR_PRTEN (1 << 13)
  157. #define UBRLCR_EVENPRT (1 << 14)
  158. #define UBRLCR_XSTOP (1 << 15)
  159. #define UBRLCR_FIFOEN (1 << 16)
  160. #define UBRLCR_WRDLEN5 (0 << 17)
  161. #define UBRLCR_WRDLEN6 (1 << 17)
  162. #define UBRLCR_WRDLEN7 (2 << 17)
  163. #define UBRLCR_WRDLEN8 (3 << 17)
  164. #define UBRLCR_WRDLEN_MASK (3 << 17)
  165. #define SYNCIO_SMCKEN (1 << 13)
  166. #define SYNCIO_TXFRMEN (1 << 14)
  167. #define SYSCON3 0x2200 /* System Control register 3 ----------------------- */
  168. #define ADCCON 0x00000001 /* ADC configuration */
  169. #define CLKCTL 0x00000006 /* processor clock control */
  170. #define CLKCTL_18 0x0 /* 18.432 MHz */
  171. #define CLKCTL_36 0x2 /* 36.864 MHz */
  172. #define CLKCTL_49 0x4 /* 49.152 MHz */
  173. #define CLKCTL_73 0x6 /* 73.728 MHz */
  174. #define MCPSEL 0x00000008 /* MCP select */
  175. #define ADCCKNSEN 0x000010 /* ADC clock sense */
  176. #define VERSN 0x000000e0 /* additional version bits */
  177. #define VERSN_SHIFT 5
  178. #define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */
  179. #define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */
  180. #define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */
  181. #define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */
  182. #define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */
  183. #define LEDFLSH_RATE 0x03 /* flash rate */
  184. #define LEDFLSH_RATE_SHIFT 0
  185. #define LEDFLSH_DUTY 0x3c /* duty ratio */
  186. #define LEDFLSH_DUTY_SHIFT 2
  187. #define LEDFLSH_ENABLE 0x40 /* enable */
  188. #define IO_START CLPS7111_PHYS_BASE
  189. #define IO(offset) (IO_START + (offset))
  190. #define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset)))
  191. #define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset)))
  192. #define IO_PADR IO_BYTE(PADR)
  193. #define IO_PBDR IO_BYTE(PBDR)
  194. #define IO_PDDR IO_BYTE(PDDR)
  195. #define IO_PADDR IO_BYTE(PADDR)
  196. #define IO_PBDDR IO_BYTE(PBDDR)
  197. #define IO_PDDDR IO_BYTE(PDDDR)
  198. #define IO_PEDR IO_BYTE(PEDR)
  199. #define IO_PEDDR IO_BYTE(PEDDR)
  200. #define IO_SYSCON IO_WORD(SYSCON)
  201. #define IO_SYSFLG IO_WORD(SYSFLG)
  202. #define IO_MEMCFG1 IO_WORD(MEMCFG1)
  203. #define IO_MEMCFG2 IO_WORD(MEMCFG2)
  204. #define IO_DRFPR IO_WORD(DRFPR)
  205. #define IO_INTSR IO_WORD(INTSR)
  206. #define IO_INTMR IO_WORD(INTMR)
  207. #define IO_LCDCON IO_WORD(LCDCON)
  208. #define IO_TC1D IO_WORD(TC1D)
  209. #define IO_TC2D IO_WORD(TC2D)
  210. #define IO_RTCDR IO_WORD(RTCDR)
  211. #define IO_RTCMR IO_WORD(RTCMR)
  212. #define IO_PMPCON IO_WORD(PMPCON)
  213. #define IO_CODR IO_BYTE(CODR)
  214. #define IO_UARTDR IO_WORD(UARTDR)
  215. #define IO_UBRLCR IO_WORD(UBRLCR)
  216. #define IO_SYNCIO IO_WORD(SYNCIO)
  217. #define IO_PALLSW IO_WORD(PALLSW)
  218. #define IO_PALMSW IO_WORD(PALMSW)
  219. #define IO_STFCLR IO_WORD(STFCLR)
  220. #define IO_BLEOI IO_WORD(BLEOI)
  221. #define IO_MCEOI IO_WORD(MCEOI)
  222. #define IO_TEOI IO_WORD(TEOI)
  223. #define IO_TC1EOI IO_WORD(TC1EOI)
  224. #define IO_TC2EOI IO_WORD(TC2EOI)
  225. #define IO_RTCEOI IO_WORD(RTCEOI)
  226. #define IO_UMSEOI IO_WORD(UMSEOI)
  227. #define IO_COEOI IO_WORD(COEOI)
  228. #define IO_HALT IO_WORD(HALT)
  229. #define IO_STDBY IO_WORD(STDBY)
  230. #define IO_SYSCON1 IO_WORD(SYSCON1)
  231. #define IO_SYSFLG1 IO_WORD(SYSFLG1)
  232. #define IO_INTSR1 IO_WORD(INTSR1)
  233. #define IO_INTMR1 IO_WORD(INTMR1)
  234. #define IO_UARTDR1 IO_WORD(UARTDR1)
  235. #define IO_UBRLCR1 IO_WORD(UBRLCR1)
  236. #define IO_FRBADDR IO_WORD(FRBADDR)
  237. #define IO_SYSCON2 IO_WORD(SYSCON2)
  238. #define IO_SYSFLG2 IO_WORD(SYSFLG2)
  239. #define IO_INTSR2 IO_WORD(INTSR2)
  240. #define IO_INTMR2 IO_WORD(INTMR2)
  241. #define IO_UARTDR2 IO_WORD(UARTDR2)
  242. #define IO_UBRLCR2 IO_WORD(UBRLCR2)
  243. #define IO_KBDEOI IO_WORD(KBDEOI)
  244. #define IO_MCCR IO_WORD(MCCR)
  245. #define IO_MCDR0 IO_WORD(MCDR0)
  246. #define IO_MCDR1 IO_WORD(MCDR1)
  247. #define IO_MCDR2 IO_WORD(MCDR2)
  248. #define IO_MCSR IO_WORD(MCSR)
  249. #define IO_SYSCON3 IO_WORD(SYSCON3)
  250. #define IO_INTSR3 IO_WORD(INTSR3)
  251. #define IO_INTMR3 IO_WORD(INTMR3)
  252. #define IO_LEDFLSH IO_WORD(LEDFLSH)
  253. #endif /* __ASM_HARDWARE_CLPS7111_H */