ahci.h 6.6 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  3. * Author: Jason Jin<Jason.jin@freescale.com>
  4. * Zhang Wei<wei.zhang@freescale.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. */
  25. #ifndef _AHCI_H_
  26. #define _AHCI_H_
  27. #define AHCI_PCI_BAR 0x24
  28. #define AHCI_MAX_SG 56 /* hardware max is 64K */
  29. #define AHCI_CMD_SLOT_SZ 32
  30. #define AHCI_RX_FIS_SZ 256
  31. #define AHCI_CMD_TBL_HDR 0x80
  32. #define AHCI_CMD_TBL_CDB 0x40
  33. #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
  34. #define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \
  35. + AHCI_RX_FIS_SZ
  36. #define AHCI_CMD_ATAPI (1 << 5)
  37. #define AHCI_CMD_WRITE (1 << 6)
  38. #define AHCI_CMD_PREFETCH (1 << 7)
  39. #define AHCI_CMD_RESET (1 << 8)
  40. #define AHCI_CMD_CLR_BUSY (1 << 10)
  41. #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
  42. /* Global controller registers */
  43. #define HOST_CAP 0x00 /* host capabilities */
  44. #define HOST_CTL 0x04 /* global host control */
  45. #define HOST_IRQ_STAT 0x08 /* interrupt status */
  46. #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
  47. #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
  48. /* HOST_CTL bits */
  49. #define HOST_RESET (1 << 0) /* reset controller; self-clear */
  50. #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
  51. #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
  52. /* Registers for each SATA port */
  53. #define PORT_LST_ADDR 0x00 /* command list DMA addr */
  54. #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
  55. #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
  56. #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
  57. #define PORT_IRQ_STAT 0x10 /* interrupt status */
  58. #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
  59. #define PORT_CMD 0x18 /* port command */
  60. #define PORT_TFDATA 0x20 /* taskfile data */
  61. #define PORT_SIG 0x24 /* device TF signature */
  62. #define PORT_CMD_ISSUE 0x38 /* command issue */
  63. #define PORT_SCR 0x28 /* SATA phy register block */
  64. #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
  65. #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
  66. #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
  67. #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
  68. /* PORT_IRQ_{STAT,MASK} bits */
  69. #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
  70. #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
  71. #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
  72. #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
  73. #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
  74. #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
  75. #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
  76. #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
  77. #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
  78. #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
  79. #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
  80. #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
  81. #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
  82. #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
  83. #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
  84. #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
  85. #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
  86. #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
  87. | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
  88. #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
  89. | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
  90. | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
  91. | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
  92. | PORT_IRQ_D2H_REG_FIS
  93. /* PORT_CMD bits */
  94. #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
  95. #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
  96. #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
  97. #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
  98. #define PORT_CMD_CLO (1 << 3) /* Command list override */
  99. #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
  100. #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
  101. #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
  102. #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
  103. #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
  104. #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
  105. #define AHCI_MAX_PORTS 32
  106. /* SETFEATURES stuff */
  107. #define SETFEATURES_XFER 0x03
  108. #define XFER_UDMA_7 0x47
  109. #define XFER_UDMA_6 0x46
  110. #define XFER_UDMA_5 0x45
  111. #define XFER_UDMA_4 0x44
  112. #define XFER_UDMA_3 0x43
  113. #define XFER_UDMA_2 0x42
  114. #define XFER_UDMA_1 0x41
  115. #define XFER_UDMA_0 0x40
  116. #define XFER_MW_DMA_2 0x22
  117. #define XFER_MW_DMA_1 0x21
  118. #define XFER_MW_DMA_0 0x20
  119. #define XFER_SW_DMA_2 0x12
  120. #define XFER_SW_DMA_1 0x11
  121. #define XFER_SW_DMA_0 0x10
  122. #define XFER_PIO_4 0x0C
  123. #define XFER_PIO_3 0x0B
  124. #define XFER_PIO_2 0x0A
  125. #define XFER_PIO_1 0x09
  126. #define XFER_PIO_0 0x08
  127. #define XFER_PIO_SLOW 0x00
  128. #define ATA_FLAG_SATA (1 << 3)
  129. #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
  130. #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
  131. #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
  132. #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
  133. #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
  134. struct ahci_cmd_hdr {
  135. u32 opts;
  136. u32 status;
  137. u32 tbl_addr;
  138. u32 tbl_addr_hi;
  139. u32 reserved[4];
  140. };
  141. struct ahci_sg {
  142. u32 addr;
  143. u32 addr_hi;
  144. u32 reserved;
  145. u32 flags_size;
  146. };
  147. struct ahci_ioports {
  148. u32 cmd_addr;
  149. u32 scr_addr;
  150. u32 port_mmio;
  151. struct ahci_cmd_hdr *cmd_slot;
  152. struct ahci_sg *cmd_tbl_sg;
  153. u32 cmd_tbl;
  154. u32 rx_fis;
  155. };
  156. struct ahci_probe_ent {
  157. pci_dev_t dev;
  158. struct ahci_ioports port[AHCI_MAX_PORTS];
  159. u32 n_ports;
  160. u32 hard_port_no;
  161. u32 host_flags;
  162. u32 host_set_flags;
  163. u32 mmio_base;
  164. u32 pio_mask;
  165. u32 udma_mask;
  166. u32 flags;
  167. u32 cap; /* cache of HOST_CAP register */
  168. u32 port_map; /* cache of HOST_PORTS_IMPL reg */
  169. u32 link_port_map; /*linkup port map*/
  170. };
  171. #endif