README.sbc8548 6.4 KB

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  1. Intro:
  2. ======
  3. The SBC8548 is a stand alone single board computer with a 1GHz
  4. MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
  5. memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
  6. and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
  7. ethernet connections.
  8. U-boot Configuration:
  9. =====================
  10. The following possible u-boot configuration targets are available:
  11. 1) sbc8548_config
  12. 2) sbc8548_PCI_33_config
  13. 3) sbc8548_PCI_66_config
  14. 4) sbc8548_PCI_33_PCIE_config
  15. 5) sbc8548_PCI_66_PCIE_config
  16. Generally speaking, most people should choose to use #5. Details
  17. of each choice are listed below.
  18. Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
  19. will be left empty (M66EN high), and so the board will operate with
  20. a base clock of 66MHz. Note that you need both PCI enabled in u-boot
  21. and linux in order to have functional PCI under linux.
  22. The second enables PCI support and builds for a 33MHz clock rate. Note
  23. that if a 33MHz 32bit card is inserted in the slot, then the whole board
  24. will clock down to a 33MHz base clock instead of the default 66MHz. This
  25. will change the baud clocks and mess up your serial console output if you
  26. were previously running at 66MHz. If you want to use a 33MHz PCI card,
  27. then you should build a U-Boot with a _PCI_33_ config and store this
  28. to flash prior to powering down the board and inserting the 33MHz PCI
  29. card. [The above discussion assumes that the SW2[1-4] has not been changed
  30. to reflect a different CCB:SYSCLK ratio]
  31. The third option builds PCI support in, and leaves the clocking at the
  32. default 66MHz. Options four and five are just repeats of option two
  33. and three, but with PCI-e support enabled as well.
  34. PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
  35. is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
  36. a 33MHz PCI configuration is currently untested.)
  37. => pci 0
  38. Scanning PCI devices on bus 0
  39. BusDevFun VendorId DeviceId Device Class Sub-Class
  40. _____________________________________________________________
  41. 00.00.00 0x1057 0x0012 Processor 0x20
  42. 00.01.00 0x8086 0x1026 Network controller 0x00
  43. => pci 1
  44. Scanning PCI devices on bus 1
  45. BusDevFun VendorId DeviceId Device Class Sub-Class
  46. _____________________________________________________________
  47. 01.00.00 0x1957 0x0012 Processor 0x20
  48. => pci 2
  49. Scanning PCI devices on bus 2
  50. BusDevFun VendorId DeviceId Device Class Sub-Class
  51. _____________________________________________________________
  52. 02.00.00 0x1148 0x9e00 Network controller 0x00
  53. =>
  54. Updating U-boot with U-boot:
  55. ============================
  56. Note that versions of u-boot up to and including 2009.08 had u-boot stored
  57. at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
  58. 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
  59. update u-boot with u-boot and it uses the old address, you will render
  60. your board inoperable, and you will require JTAG recovery.
  61. The following steps list how to update with the current address:
  62. tftp u-boot.bin
  63. md 200000 10
  64. protect off all
  65. erase fffa0000 ffffffff
  66. cp.b 200000 fffa0000 60000
  67. md fffa0000 10
  68. protect on all
  69. The "md" steps in the above are just a precautionary step that allow
  70. you to confirm the u-boot version that was downloaded, and then confirm
  71. that it was copied to flash.
  72. Hardware Reference:
  73. ===================
  74. The following contains some summary information on hardware settings
  75. that are relevant to u-boot, based on the board manual. For the
  76. most up to date and complete details of the board, please request the
  77. reference manual ERG-00327-001.pdf from www.windriver.com
  78. Boot flash:
  79. intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
  80. Sodimm flash:
  81. intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
  82. Jumpers:
  83. Jumper Name ON OFF
  84. ----------------------------------------------------------------
  85. JP12 CS0/CS6 swap see note[*] see note[*]
  86. JP13 SODIMM flash write OK writes disabled
  87. write prot.
  88. JP14 HRESET/TRST joined isolated
  89. JP15 PWR ON when AC pwr use S1 for on/off
  90. JP16 Demo LEDs lit not lit
  91. JP19 PCI mode PCI PCI-X
  92. [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
  93. onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
  94. is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
  95. SODIMM flash and /CS6 is for the boot flash. Note that in this
  96. alternate setting, you also need to switch SW2.8 to ON. Currently
  97. u-boot doesn't support booting off the SODIMM in this alternate
  98. setting without manually altering BR0/OR0 and BR6/OR6 in the
  99. board config file appropriately.
  100. Switches:
  101. The defaults are marked with a *
  102. Name Desc. ON OFF
  103. ------------------------------------------------------------------
  104. S1 Pwr toggle n/a n/a
  105. SW2.1 CFG_SYS_PLL0 1 0*
  106. SW2.2 CFG_SYS_PLL1 1* 0
  107. SW2.3 CFG_SYS_PLL2 1* 0
  108. SW2.4 CFG_SYS_PLL3 1 0*
  109. SW2.5 CFG_CORE_PLL0 1* 0
  110. SW2.6 CFG_CORE_PLL1 1 0*
  111. SW2.7 CFG_CORE_PLL2 1* 0
  112. SW2.8 CFG_ROM_LOC1 1 0*
  113. SW3.1 CFG_HOST_AGT0 1* 0
  114. SW3.2 CFG_HOST_AGT1 1* 0
  115. SW3.3 CFG_HOST_AGT2 1* 0
  116. SW3.4 CFG_IO_PORTS0 1* 0
  117. SW3.5 CFG_IO_PORTS0 1 0*
  118. SW3.6 CFG_IO_PORTS0 1 0*
  119. SerDes CLK(MHz) SW5.1 SW5.2
  120. ----------------------------------------------
  121. 25 0 0
  122. 100* 1 0
  123. 125 0 1
  124. 200 1 1
  125. SerDes CLK spread SW5.3 SW5.4
  126. ----------------------------------------------
  127. +/- 0.25% 0 0
  128. -0.50% 1 0
  129. -0.75% 0 1
  130. No Spread* 1 1
  131. SW4 settings are readable from the EPLD and are currently not used for
  132. any hardware settings (i.e. user configuration switches).
  133. LEDs:
  134. Name Desc. ON OFF
  135. ------------------------------------------------------------------
  136. D13 PCI/PCI-X PCI-X PCI
  137. D14 3.3V PWR 3.3V no power
  138. D15 SYSCLK 66MHz 33MHz
  139. Default Memory Map:
  140. start end CS<n> width Desc.
  141. ----------------------------------------------------------------------
  142. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
  143. f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
  144. f800_0000 f8b0_1fff CS5 - EPLD
  145. fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
  146. ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
  147. The EPLD on CS5 demuxes the following devices at the following offsets:
  148. offset size width device
  149. --------------------------------------------------------
  150. 0 1fff 8 7 segment display LED
  151. 10_0000 1fff 4 user switches
  152. 30_0000 1fff 4 HW Rev. register
  153. b0_0000 1fff 8 8kB EEPROM