README.ocotea 1.8 KB

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  1. AMCC Ocotea Board
  2. Last Update: March 2, 2004
  3. =======================================================================
  4. This file contains some handy info regarding U-Boot and the AMCC
  5. Ocotea 440gx evalutation board. See the README.ppc440 for additional
  6. information.
  7. SWITCH SETTINGS & JUMPERS
  8. ==========================
  9. Here's what I've been using successfully. If you feel inclined to
  10. change things ... please read the docs!
  11. DIPSW U46 U80
  12. ------------------------
  13. SW 1 off off
  14. SW 2 on off
  15. SW 3 off off
  16. SW 4 off off
  17. SW 5 off off
  18. SW 6 on on
  19. SW 7 on off
  20. SW 8 on off
  21. J41: strapped
  22. J42: open
  23. All others are factory default.
  24. I2C Information
  25. =====================
  26. See README.ebony for information.
  27. PCI
  28. ===========================
  29. Untested at the time of writing.
  30. PPC440GX Ethernet EMACs
  31. ===========================
  32. All EMAC ports have been tested and are known to work
  33. with EPS Group 4.
  34. Special note about the Cicada CIS8201:
  35. The CIS8201 Gigabit PHY comes up in GMII mode by default.
  36. One must hit an extended register to allow use of RGMII mode.
  37. This has been done in the 440gx_enet.c file with a #ifdef/endif
  38. pair.
  39. AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
  40. The addresses contained in the config header file are from my particular
  41. board and you _*should*_ change them to reflect your board either in the
  42. config file and/or in your environment variables. I found the addresses on
  43. labels on the bottom side of the board.
  44. BDI2k or JTAG Debugging
  45. ===========================
  46. For ease of debugging you can swap the small boot flash and external SRAM
  47. by changing U46:3 to on. You can then use the sram as your boot flash by
  48. loading the sram via the jtag debugger.
  49. Regards,
  50. --Travis
  51. <tsawyer@sandburst.com>