README.mpc8641hpcn 5.9 KB

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  1. Freescale MPC8641HPCN board
  2. ===========================
  3. Created 05/24/2006 Haiying Wang
  4. -------------------------------
  5. 1. Building U-Boot
  6. ------------------
  7. The 86xx HPCN code base is known to compile using:
  8. Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
  9. $ make MPC8641HPCN_config
  10. Configuring for MPC8641HPCN board...
  11. $ make
  12. 2. Switch and Jumper Setting
  13. ----------------------------
  14. Jumpers:
  15. J14 Pins 1-2 (near plcc32 socket)
  16. Switches:
  17. SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
  18. 01100 :: CORE = 2.5:1
  19. 10000 :: CORE = 3:1
  20. 11100 :: CORE = 3.5:1
  21. 10100 :: CORE = 4:1
  22. 01110 :: CORE = 4.5:1
  23. SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
  24. 001 :: SYSCLK = 40MHz
  25. SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
  26. 0100 :: 4X
  27. 0110 :: 6X
  28. 1000 :: 8X
  29. 1010 :: 10X
  30. 1100 :: 12X
  31. 1110 :: 14X
  32. 0000 :: 16X
  33. SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
  34. SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
  35. 0100000 :: VCORE = 1.11V
  36. SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
  37. 1 :: VCC_PLAT = 1.0V
  38. SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
  39. SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
  40. SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
  41. SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
  42. 0 :: boot from PromJet
  43. SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
  44. halves (virtual banks)
  45. 0 :: normal
  46. SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
  47. SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
  48. 1:1 for PD6
  49. SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
  50. SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
  51. SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
  52. SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
  53. SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
  54. SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
  55. SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
  56. SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
  57. SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
  58. SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
  59. SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
  60. SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
  61. SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
  62. SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
  63. SW8(7) = 1 ACPWR = 1 :: non-battery
  64. SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
  65. 3. Flash U-Boot
  66. ---------------
  67. The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
  68. It is possible to use either half to boot using u-boot. Switch 5 bit 2
  69. is used for this purpose.
  70. 0xEF800000 to 0xEFBFFFFF - 4MB
  71. 0xEFC00000 to 0xEFFFFFFF - 4MB
  72. When this bit is 0, U-Boot is at 0xEFF00000.
  73. When this bit is 1, U-Boot is at 0xEFB00000.
  74. Use the above mentioned flash commands to program the other half, and
  75. use switch 5, bit 2 to alternate between the halves. Note: The booting
  76. version of U-Boot will always be at 0xEFF00000.
  77. To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
  78. tftp 1000000 u-boot.bin
  79. protect off all
  80. erase eff00000 +$filesize
  81. cp.b 1000000 eff00000 $filesize
  82. or use tftpflash command:
  83. run tftpflash
  84. To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
  85. tftp 1000000 u-boot.bin
  86. erase efb00000 +$filesize
  87. cp.b 1000000 efb00000 $filesize
  88. 4. Memory Map
  89. -------------
  90. NOTE: RIO and PCI are mutually exclusive, so they share an address
  91. For 32-bit u-boot, devices are mapped so that the virtual address ==
  92. the physical address, and the map looks liks this:
  93. Memory Range Device Size
  94. ------------ ------ ----
  95. 0x0000_0000 0x7fff_ffff DDR 2G
  96. 0x8000_0000 0x9fff_ffff RIO MEM 512M
  97. 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
  98. 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
  99. 0xffe0_0000 0xffef_ffff CCSR 1M
  100. 0xffdf_0000 0xffdf_7fff PIXIS 8K
  101. 0xffdf_8000 0xffdf_ffff CF 8K
  102. 0xf840_0000 0xf840_3fff Stack space 32K
  103. 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
  104. 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
  105. 0xef80_0000 0xefff_ffff Flash 8M
  106. For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
  107. However, the physical map is altered to reside in 36-bit space, as follows.
  108. Addresses are no longer mapped with VA == PA. All accesses from
  109. software use the VA; the PA is only used for setting up windows
  110. and mappings. Note that with the exception of PCI MEM and RIO, the low
  111. 32 bits are the same as the VA above; only the top 4 bits vary:
  112. Memory Range Device Size
  113. ------------ ------ ----
  114. 0x0_0000_0000 0x0_7fff_ffff DDR 2G
  115. 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
  116. 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
  117. 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
  118. 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
  119. 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
  120. 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
  121. 0x0_f840_0000 0xf_f840_3fff Stack space 32K
  122. 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
  123. 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
  124. 0xf_ef80_0000 0xf_efff_ffff Flash 8M
  125. 5. pixis_reset command
  126. --------------------
  127. A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
  128. using the FPGA sequencer. When the board restarts, it has the option
  129. of using either the current or alternate flash bank as the boot
  130. image, with or without the watchdog timer enabled, and finally with
  131. or without frequency changes.
  132. Usage is;
  133. pixis_reset
  134. pixis_reset altbank
  135. pixis_reset altbank wd
  136. pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
  137. pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
  138. Examples;
  139. /* reset to current bank, like "reset" command */
  140. pixis_reset
  141. /* reset board but use the to alternate flash bank */
  142. pixis_reset altbank
  143. /* reset board, use alternate flash bank with watchdog timer enabled*/
  144. pixis_reset altbank wd
  145. /* reset board to alternate bank with frequency changed.
  146. * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
  147. */
  148. pixis-reset altbank cf 40 2.5 10
  149. Valid clock choices are in the 8641 Reference Manuals.