README.mpc7448hpc2 4.3 KB

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  1. Freescale MPC7448hpc2 (Taiga) board
  2. ===================================
  3. Created 08/11/2006 Roy Zang
  4. --------------------------
  5. MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
  6. design, which is optimized for high speed throughput between the processor and
  7. the memory, disk drive and Ethernet port subsystems.
  8. MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
  9. used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
  10. chassis.
  11. Building U-Boot
  12. ------------------
  13. The mpc7448hpc2 code base is known to compile using:
  14. Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
  15. $ make mpc7448hpc2_config
  16. Configuring for mpc7448hpc2 board...
  17. $ make
  18. Memory Map
  19. ----------
  20. The memory map is setup for Linux to operate properly.
  21. The mapping is:
  22. Range Start Range End Definition Size
  23. 0x0000_0000 0x7fff_ffff DDR 2G
  24. 0xe000_0000 0xe7ff_ffff PCI Memory 128M
  25. 0xfa00_0000 0xfaff_ffff PCI IO 16M
  26. 0xfb00_0000 0xfbff_ffff PCI Config 16M
  27. 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
  28. 0xfe00_0000 0xfeff_ffff PromJet 16M
  29. 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
  30. 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
  31. Using Flash
  32. -----------
  33. The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
  34. (2^23 = 0x00800000).
  35. Note: the "bank" here refers to half of the flash. In fact, there is only one
  36. bank of flash, which is divided into low and high half. Each is controlled by
  37. the most significant bit of the address bus. The so called "bank" is only for
  38. convenience.
  39. There is a switch which allows the "bank" to be selected. The switch
  40. settings for updating flash are given below.
  41. The u-boot commands for copying the boot-bank into the secondary bank are
  42. as follows:
  43. erase ff800000 ff880000
  44. cp.b ff000000 ff800000 80000
  45. U-boot commands for downloading an image via tftp and flashing
  46. it into the secondary bank:
  47. tftp 10000 <u-boot.bin.image>
  48. erase ff000000 ff080000
  49. cp.b 10000 ff000000 80000
  50. After copying the image into the second bank of flash, be sure to toggle
  51. SW3[4] on board before resetting the board in order to set the
  52. secondary bank as the boot-bank.
  53. Board Switches
  54. ----------------------
  55. Most switches on the board should not be changed. The most frequent
  56. user-settable switches on the board are used to configure
  57. the flash banks and determining the PCI frequency.
  58. SW1[1-5]: Processor core voltage
  59. 12345 Core Voltage
  60. -----
  61. SW1=01111 1.000V.
  62. SW1=01101 1.100V.
  63. SW1=01011 1.200V.
  64. SW1=01001 1.300V only for MPC7447A.
  65. SW2[1-6]: CPU core frequency
  66. CPU Core Frequency (MHz)
  67. Bus Frequency
  68. 123456 100 133 167 200 Ratio
  69. ------
  70. SW2=101100 500 667 833 1000 5x
  71. SW2=100100 550 733 917 1100 5.5x
  72. SW2=110100 600 800 1000 1200 6x
  73. SW2=010100 650 866 1083 1300 6.5x
  74. SW2=001000 700 930 1167 1400 7x
  75. SW2=000100 750 1000 1250 1500 7.5x
  76. SW2=110000 800 1066 1333 1600 8x
  77. SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
  78. SW2=011110 900 1200 1500 1800 9x
  79. This table shows only a subset of available frequency options; see the CPU
  80. hardware specifications for more information.
  81. SW2[7-8]: Bus Protocol and CPU Reset Option
  82. 7
  83. -
  84. SW2=0 System bus uses MPX bus protocol
  85. SW2=1 System bus uses 60x bus protocol
  86. 8
  87. -
  88. SW2=0 TSI108 can cause CPU reset
  89. SW2=1 TSI108 can not cause CPU reset
  90. SW3[1-8] system options
  91. 123
  92. ---
  93. SW3=xxx Connected to GPIO[0:2] on TSI108
  94. 4
  95. -
  96. SW3=0 CPU boots from low half of flash
  97. SW3=1 CPU boots from high half of flash
  98. 5
  99. -
  100. SW3=0 SATA and slot2 connected to PCI bus
  101. SW3=1 Only slot1 connected to PCI bus
  102. 6
  103. -
  104. SW3=0 USB connected to PCI bus
  105. SW3=1 USB disconnected from PCI bus
  106. 7
  107. -
  108. SW3=0 Flash is write protected
  109. SW3=1 Flash is NOT write protected
  110. 8
  111. -
  112. SW3=0 CPU will boot from flash
  113. SW3=1 CPU will boot from PromJet
  114. SW4[1-3]: System bus frequency
  115. Bus Frequency (MHz)
  116. ---
  117. SW4=010 183
  118. SW4=011 100
  119. SW4=100 133
  120. SW4=101 166 only for MPC7447A
  121. SW4=110 200 only for MPC7448
  122. others reserved
  123. SW4[4-6]: DDR2 SDRAM frequency
  124. Bus Frequency (MHz)
  125. ---
  126. SW4=000 external clock
  127. SW4=011 system clock
  128. SW4=100 133
  129. SW4=101 166
  130. SW4=110 200
  131. others reserved
  132. SW4[7-8]: PCI/PCI-X frequency control
  133. 7
  134. -
  135. SW4=0 PCI/PCI-X bus operates normally
  136. SW4=1 PCI bus forced to PCI-33 mode
  137. 8
  138. -
  139. SW4=0 PCI-X mode at 133 MHz allowed
  140. SW4=1 PCI-X mode limited to 100 MHz