README.mips 1.7 KB

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  1. Notes for the MIPS architecture port of U-Boot
  2. Toolchains
  3. ----------
  4. http://www.denx.de/wiki/DULG/ELDK
  5. ELDK < DULG < DENX
  6. http://www.emdebian.org/crosstools.html
  7. Embedded Debian -- Cross-development toolchains
  8. http://buildroot.uclibc.org/
  9. Buildroot
  10. Known Issues
  11. ------------
  12. * Little endian build problem
  13. If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
  14. objects will be generated in big-endian format.
  15. * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
  16. Cache will be disabled before entering the loaded ELF image without
  17. writing back and invalidating cache lines. This leads to cache
  18. incoherency in most cases, unless the code gets loaded after U-Boot
  19. re-initializes the cache. The more common uImage 'bootm' command does
  20. not suffer this problem.
  21. [workaround] To avoid this cache incoherency,
  22. 1) insert flush_cache(all) before calling dcache_disable(), or
  23. 2) fix dcache_disable() to do both flushing and disabling cache.
  24. * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
  25. or override do_bootelf_exec() not to disable I-/D-caches, because most
  26. Linux/MIPS ports don't re-enable caches after entering kernel_entry.
  27. TODOs
  28. -----
  29. * Probe CPU types, I-/D-cache and TLB size etc. automatically
  30. * Secondary cache support missing
  31. * Centralize the link directive files
  32. * Initialize TLB entries redardless of their use
  33. * R2000/R3000 class parts are not supported
  34. * Limited testing across different MIPS variants
  35. * Due to cache initialization issues, the DRAM on board must be
  36. initialized in board specific assembler language before the cache init
  37. code is run -- that is, initialize the DRAM in lowlevel_init().