README.fsl-ddr 3.2 KB

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  1. Table of interleaving modes supported in cpu/8xxx/ddr/
  2. ======================================================
  3. +-------------+---------------------------------------------------------+
  4. | | Rank Interleaving |
  5. | +--------+-----------+-----------+------------+-----------+
  6. |Memory | | | | 2x2 | 4x1 |
  7. |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  8. |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
  9. +-------------+--------+-----------+-----------+------------+-----------+
  10. |None | Yes | Yes | Yes | Yes | Yes |
  11. +-------------+--------+-----------+-----------+------------+-----------+
  12. |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
  13. | |CS0 Only| | | {CS0+CS1} | |
  14. +-------------+--------+-----------+-----------+------------+-----------+
  15. |Page | Yes | Yes | No | No, Only(*)| Yes |
  16. | |CS0 Only| | | {CS0+CS1} | |
  17. +-------------+--------+-----------+-----------+------------+-----------+
  18. |Bank | Yes | Yes | No | No, Only(*)| Yes |
  19. | |CS0 Only| | | {CS0+CS1} | |
  20. +-------------+--------+-----------+-----------+------------+-----------+
  21. |Superbank | No | Yes | No | No, Only(*)| Yes |
  22. | | | | | {CS0+CS1} | |
  23. +-------------+--------+-----------+-----------+------------+-----------+
  24. (*) Although the hardware can be configured with memory controller
  25. interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
  26. from each controller. {CS2+CS3} on each controller are only rank
  27. interleaved on that controller.
  28. The ways to configure the ddr interleaving mode
  29. ==============================================
  30. 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
  31. under "CONFIG_EXTRA_ENV_SETTINGS", like:
  32. #define CONFIG_EXTRA_ENV_SETTINGS \
  33. "memctl_intlv_ctl=2\0" \
  34. ......
  35. 2. Run u-boot "setenv" command to configure the memory interleaving mode.
  36. Either numerical or string value is accepted.
  37. # disable memory controller interleaving
  38. setenv memctl_intlv_ctl
  39. # cacheline interleaving
  40. setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline
  41. # page interleaving
  42. setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page
  43. # bank interleaving
  44. setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank
  45. # superbank
  46. setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank
  47. # disable bank (chip-select) interleaving
  48. setenv ba_intlv_ctl
  49. # bank(chip-select) interleaving cs0+cs1
  50. setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1
  51. # bank(chip-select) interleaving cs2+cs3
  52. setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3
  53. # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
  54. setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3
  55. # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
  56. setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3