README.dk1s10_mldk20 11 KB

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  1. TODO: specify IDE i/f
  2. ===============================================================================
  3. C P U , M E M O R Y , I N / O U T C O M P O N E N T S
  4. ===============================================================================
  5. see also [1]-[5]
  6. CPU: "LDK2"
  7. 32 bit NIOS for 75 MHz
  8. 512 Byte for register file (30 levels)
  9. with out instruction cache
  10. with out data cache
  11. 2 KByte On Chip ROM with GERMS boot monitor
  12. with out On Chip RAM
  13. MSTEP multiplier
  14. no Debug Core
  15. no On Chip Instrumentation (OCI)
  16. U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 75000000
  17. CONFIG_SYS_NIOS_CPU_ICACHE = (not present)
  18. CONFIG_SYS_NIOS_CPU_DCACHE = (not present)
  19. CONFIG_SYS_NIOS_CPU_REG_NUMS = 512
  20. CONFIG_SYS_NIOS_CPU_MUL = 0
  21. CONFIG_SYS_NIOS_CPU_MSTEP = 1
  22. CONFIG_SYS_NIOS_CPU_DBG_CORE = 0
  23. IRQ: Nr. | used by
  24. ------+--------------------------------------------------------
  25. 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
  26. 17 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 17
  27. 18 | UART1 | CONFIG_SYS_NIOS_CPU_UART1_IRQ = 18
  28. 20 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 20
  29. 25 | IDE0 | CONFIG_SYS_NIOS_CPU_IDE0_IRQ = 25
  30. MEMORY: 8 MByte Flash
  31. 16 MByte SDRAM
  32. Timer: TIMER0: high priority programmable timer (IRQ16)
  33. U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0
  34. CONFIG_SYS_NIOS_CPU_USER_TIMER = (not present)
  35. PIO: Nr. | description
  36. ------+--------------------------------------------------------
  37. PIO0 | CFPOWER: 1 output to controll CF power supply
  38. PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ)
  39. ------+--------------------------------------------------------
  40. not | LCD: 11 in/outputs for ASCII LCD
  41. pres.| LED: 8 outputs for user LEDs
  42. | SEVENSEG: 16 outputs for user seven segment display
  43. | RECONF: 1 in/output for . . . . . . . . . . . .
  44. | CFPRESENT: 1 input for CF present event (IRQ35)
  45. | CFATASEL: 1 output to controll CF ATA card select
  46. U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 1
  47. CONFIG_SYS_NIOS_CPU_LCD_PIO = (not present)
  48. CONFIG_SYS_NIOS_CPU_LED_PIO = (not present)
  49. CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = (not present)
  50. CONFIG_SYS_NIOS_CPU_RECONF_PIO = (not present)
  51. CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = (not present)
  52. CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 0
  53. CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = (not present)
  54. UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
  55. without handshake RTS/CTS (IRQ17)
  56. UART1: fixed baudrate of 115200, fixed protocol 8N1,
  57. without handshake RTS/CTS (IRQ18)
  58. LAN: SMsC LAN91C111 with:
  59. - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
  60. - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
  61. IDE: (TODO)
  62. ===============================================================================
  63. M E M O R Y M A P
  64. ===============================================================================
  65. - - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
  66. 0x02000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_STACK
  67. 0x02000000 --+32-----------16|15------------0+
  68. | . | \ \
  69. | . | | |
  70. | . | | > stack area
  71. | . | | |
  72. | . | | V
  73. | . | |
  74. | . | |
  75. SDRAM | . | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
  76. | . | | = 0x01000000
  77. | . | |
  78. 0x01000100 |- - - - - - - - - - - - - - - -+-|-
  79. | . | | \
  80. | . | | |
  81. | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE
  82. | . | | | = 0x00000100
  83. | | / /
  84. 0x01000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE
  85. 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE
  86. | sector 127 | \
  87. + 0x7f0000 |- - - - - - - - - - - - - - - -| |
  88. | : | |
  89. Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
  90. | sector 1 : | | = 0x00800000
  91. + 0x010000 |- - - - - - - - - - - - - - - -| |
  92. | sector 0 (size = 0x10000) | /
  93. 0x00800000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE
  94. | |
  95. : gap :
  96. : :
  97. - - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
  98. : :
  99. : gap :
  100. | |
  101. 0x00020000 ---32-----------16|15------------0-
  102. | gap | \
  103. 0x00010310 --+-------------------------------| |
  104. | | |
  105. | register bank (size = 0x10) | |
  106. | +--------.---.---.--- | |
  107. | | bank 0 \ 1 \ 2 \ 3 \ | |
  108. | |---------------------------+ | |
  109. LAN91C111 | | BANK | RESERVED | | |
  110. | |- - - - - - -|- - - - - - -| | > na_enet_size
  111. | | RPCR | MIR | | | = 0x00010000
  112. | |- - - - - - -|- - - - - - -| | |
  113. | | COUNTER | RCR | | |
  114. | |- - - - - - -|- - - - - - -| | |
  115. | | EPH STATUS | TCR | | |
  116. | +---------------------------+ | |
  117. 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| |
  118. | gap | /
  119. 0x00010000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE
  120. | |
  121. : gap :
  122. : :
  123. - - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
  124. : :
  125. : gap :
  126. | |
  127. 0x00000980 ---32-----------16|15------------0-
  128. | | | \
  129. : (real size : : |
  130. IDE i/f : and content : : > 0x00000080
  131. [5] : unknown) : : |
  132. | | | /
  133. 0x00000900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0
  134. | | \
  135. : gap : > (space for PIO4..7)
  136. | | /
  137. 0x000008c0 ---32-----------16|15------------0-
  138. | (unused) | \
  139. + 0x1c |- - - - - - - - - - - - - - - -| |
  140. | (unused) | |
  141. + 0x18 |- - - - - - - - - - - - - - - -| |
  142. | (unused) | |
  143. + 0x14 |- - - - - - - - - - - - - - - -| |
  144. UART1 | (unused) | > 0x00000020
  145. [2] + 0x10 |- - - - - - - - - - - - - - - -| |
  146. | control (10 bit) (rw) | |
  147. + 0x0c |- - - - - - - - - - - - - - - -| |
  148. | status (10 bit) (rw) | |
  149. + 0x08 |- - - - - - - - - - - - - - - -| |
  150. | txdata (8 bit) (wo) | |
  151. + 0x04 |- - - - - - - - - - - - - - - -| |
  152. | rxdata (8 bit) (ro) | /
  153. 0x000008a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART1
  154. | | \
  155. : gap : > (space for PIO2..3)
  156. | | /
  157. 0x00000880 ---32-----------16|15------------0-
  158. | edgecapture (4 bit) (rw) | \
  159. + 0x0c |- - - - - - - - - - - - - - - -| |
  160. PIO1 | interruptmask (4 bit) (rw) | |
  161. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  162. | (unused) | |
  163. + 0x04 |- - - - - - - - - - - - - - - -| |
  164. | data (4 bit) (ro) | /
  165. 0x00000870 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1
  166. | (unused) | \
  167. + 0x0c |- - - - - - - - - - - - - - - -| |
  168. PIO0 | (unused) | |
  169. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  170. | (unused) | |
  171. + 0x04 |- - - - - - - - - - - - - - - -| |
  172. | data (1 bit) (wo) | /
  173. 0x00000860 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0
  174. | (unused) | \
  175. + 0x1c |- - - - - - - - - - - - - - - -| |
  176. | (unused) | |
  177. + 0x18 |- - - - - - - - - - - - - - - -| |
  178. | snaph (16 bit) (rw) | |
  179. + 0x14 |- - - - - - - - - - - - - - - -| |
  180. TIMER0 | snapl (16 bit) (rw) | |
  181. [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
  182. | periodh (16 bit) (rw) | |
  183. + 0x0c |- - - - - - - - - - - - - - - -| |
  184. | periodl (16 bit) (rw) | |
  185. + 0x08 |- - - - - - - - - - - - - - - -| |
  186. | control (4 bit) (rw) | |
  187. + 0x04 |- - - - - - - - - - - - - - - -| |
  188. | status (2 bit) (rw) | /
  189. 0x00000840 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0
  190. | | \
  191. : gap : > (space for UART2)
  192. | | /
  193. 0x00000820 ---32-----------16|15------------0-
  194. | (unused) | \
  195. + 0x1c |- - - - - - - - - - - - - - - -| |
  196. | (unused) | |
  197. + 0x18 |- - - - - - - - - - - - - - - -| |
  198. | (unused) | |
  199. + 0x14 |- - - - - - - - - - - - - - - -| |
  200. UART0 | (unused) | > 0x00000020
  201. [2] + 0x10 |- - - - - - - - - - - - - - - -| |
  202. | control (10 bit) (rw) | |
  203. + 0x0c |- - - - - - - - - - - - - - - -| |
  204. | status (10 bit) (rw) | |
  205. + 0x08 |- - - - - - - - - - - - - - - -| |
  206. | txdata (8 bit) (wo) | |
  207. + 0x04 |- - - - - - - - - - - - - - - -| |
  208. | rxdata (8 bit) (ro) | /
  209. 0x00000800 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0
  210. - - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
  211. 0x00000800 ---32-----------16|15------------0-
  212. | : | \
  213. | : | |
  214. GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE
  215. | : | | = 0x00000800
  216. | : | /
  217. 0x00000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
  218. 0x00000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE
  219. ===============================================================================
  220. F L A S H M E M O R Y A L L O C A T I O N
  221. ===============================================================================
  222. 0x01000000 ---8-------------4|3-------------0-
  223. | : | \
  224. SAFE | : | > 1 MByte
  225. FPGA conf. | : | / (NOT usable by software)
  226. 0x00f00000 --+- - - - - - - -:- - - - - - - -+-
  227. | : | \
  228. USER | : | > 1 MByte
  229. FPGA conf. | : | / (NOT usable by software)
  230. 0x00e00000 --+- - - - - - - -:- - - - - - - -+-
  231. | : | \
  232. | : | |
  233. WEB pages | : | > 2 MByte
  234. | : | | (provisory usable)
  235. | : | /
  236. 0x00c00000 --+- - - - - - - -:- - - - - - - -+-
  237. | : | \
  238. | : | |
  239. | : | |
  240. | : | > 4 MByte free for use
  241. | : | |
  242. 0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
  243. | : | /
  244. 0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start()
  245. 0x00800000 ---8-------------4|3-------------0-
  246. ===============================================================================
  247. R E F E R E N C E S
  248. ===============================================================================
  249. [1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
  250. [2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
  251. [3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
  252. [4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
  253. [5] http://www.opencores.org/projects/ata/
  254. http://www.t13.org/index.html
  255. ===============================================================================
  256. Stephan Linz <linz@li-pro.net>