README.dk1c20_std32 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366
  1. TODO: specify IDE i/f
  2. specify ASMI i/f
  3. specify OCI
  4. ===============================================================================
  5. C P U , M E M O R Y , I N / O U T C O M P O N E N T S
  6. ===============================================================================
  7. see also [1]-[6]
  8. CPU: "standard_32"
  9. 32 bit NIOS for 50 MHz
  10. 256 Byte for register file (15 levels)
  11. 4 KByte instruction cache (2 bytes in each cache line)
  12. 4 KByte data cache (4 bytes in each cache line)
  13. 2 KByte On Chip ROM with GERMS boot monitor
  14. no On Chip RAM
  15. MSTEP multiplier
  16. no Debug Core
  17. On Chip Instrumentation (OCI) enabled
  18. U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000
  19. CONFIG_SYS_NIOS_CPU_ICACHE = 4096
  20. CONFIG_SYS_NIOS_CPU_DCACHE = 4096
  21. CONFIG_SYS_NIOS_CPU_REG_NUMS = 256
  22. CONFIG_SYS_NIOS_CPU_MUL = 0
  23. CONFIG_SYS_NIOS_CPU_MSTEP = 1
  24. CONFIG_SYS_NIOS_CPU_DBG_CORE = 0
  25. OCI: (TODO)
  26. IRQ: Nr. | used by
  27. ------+--------------------------------------------------------
  28. 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
  29. 25 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25
  30. 30 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30
  31. 35 | PIO5 | CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35
  32. 40 | PIO0 | CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40
  33. 45 | ASMI | CONFIG_SYS_NIOS_CPU_ASMI0_IRQ = 45
  34. 50 | TIMER1 | CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
  35. MEMORY: 8 MByte Flash
  36. 1 MByte SRAM
  37. 16 MByte SDRAM
  38. ASMI: (TODO) <-- ASMI part is 4M bits
  39. Timer: TIMER0: high priority programmable timer (IRQ16)
  40. TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
  41. U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1
  42. CONFIG_SYS_NIOS_CPU_USER_TIMER = 0
  43. PIO: Nr. | description
  44. ------+--------------------------------------------------------
  45. PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
  46. PIO1 | LCD: 11 in/outputs for ASCII LCD
  47. PIO2 | LED: 8 outputs for user LEDs
  48. PIO3 | SEVENSEG: 16 outputs for user seven segment display
  49. PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
  50. PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
  51. PIO6 | CFPOWER: 1 output to controll CF power supply
  52. PIO7 | CFATASEL: 1 output to controll CF ATA card select
  53. U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0
  54. CONFIG_SYS_NIOS_CPU_LCD_PIO = 1
  55. CONFIG_SYS_NIOS_CPU_LED_PIO = 2
  56. CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3
  57. CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4
  58. CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5
  59. CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6
  60. CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7
  61. UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
  62. without handshake RTS/CTS (IRQ25)
  63. LAN: SMsC LAN91C111 with:
  64. - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
  65. - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
  66. IDE: (TODO)
  67. ===============================================================================
  68. M E M O R Y M A P
  69. ===============================================================================
  70. - - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
  71. 0x02000000 ---32-----------16|15------------0-
  72. | : | \
  73. | : | |
  74. SDRAM | : | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
  75. | : | | = 0x01000000
  76. | : | /
  77. 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE
  78. | |
  79. : gap :
  80. : :
  81. - - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
  82. : :
  83. : gap :
  84. | |
  85. 0x________ ---32-----------16|15------------0-
  86. | | | \
  87. : (real size : : |
  88. ASMI i/f : and content : : > 0x________
  89. [5] : unknown) : : |
  90. | | | /
  91. 0x00920b00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ASMI0
  92. | |
  93. : gap :
  94. | |
  95. 0x00920a80 ---32-----------16|15------------0-
  96. | | | \
  97. : (real size : : |
  98. IDE i/f : and content : : > 0x00000080
  99. [6] : unknown) : : |
  100. | | | /
  101. 0x00920a00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0
  102. | (unused) | \
  103. + 0x1c |- - - - - - - - - - - - - - - -| |
  104. | (unused) | |
  105. + 0x18 |- - - - - - - - - - - - - - - -| |
  106. | (unused) | |
  107. + 0x14 |- - - - - - - - - - - - - - - -| |
  108. TIMER1 | (unused) | |
  109. [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
  110. | (unused) | |
  111. + 0x0c |- - - - - - - - - - - - - - - -| |
  112. | (unused) | |
  113. + 0x08 |- - - - - - - - - - - - - - - -| |
  114. | control (1 bit) (rw) | |
  115. + 0x04 |- - - - - - - - - - - - - - - -| |
  116. | status (2 bit) (rw) | /
  117. 0x009209e0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1
  118. | (unused) | \
  119. + 0x0c |- - - - - - - - - - - - - - - -| |
  120. PIO7 | (unused) | |
  121. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  122. | (unused) | |
  123. + 0x04 |- - - - - - - - - - - - - - - -| |
  124. | data (1 bit) (wo) | /
  125. 0x009209d0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7
  126. | (unused) | \
  127. + 0x0c |- - - - - - - - - - - - - - - -| |
  128. PIO6 | (unused) | |
  129. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  130. | (unused) | |
  131. + 0x04 |- - - - - - - - - - - - - - - -| |
  132. | data (1 bit) (wo) | /
  133. 0x009209c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6
  134. | edgecapture (1 bit) (rw) | \
  135. + 0x0c |- - - - - - - - - - - - - - - -| |
  136. PIO5 | interruptmask (1 bit) (rw) | |
  137. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  138. | (unused) | |
  139. + 0x04 |- - - - - - - - - - - - - - - -| |
  140. | data (1 bit) (ro) | /
  141. 0x009209b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5
  142. | (unused) | \
  143. + 0x0c |- - - - - - - - - - - - - - - -| |
  144. PIO4 | (unused) | |
  145. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  146. | direction (1 bit) (rw) | |
  147. + 0x04 |- - - - - - - - - - - - - - - -| |
  148. | data (1 bit) (rw) | /
  149. 0x009209a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4
  150. | (unused) | \
  151. + 0x0c |- - - - - - - - - - - - - - - -| |
  152. PIO3 | (unused) | |
  153. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  154. | (unused) | |
  155. + 0x04 |- - - - - - - - - - - - - - - -| |
  156. | data (16 bit) (wo) | /
  157. 0x00920990 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3
  158. | (unused) | \
  159. + 0x0c |- - - - - - - - - - - - - - - -| |
  160. PIO2 | (unused) | |
  161. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  162. | (unused) | |
  163. + 0x04 |- - - - - - - - - - - - - - - -| |
  164. | data (8 bit) (wo) | /
  165. 0x00920980 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2
  166. | (unused) | \
  167. + 0x0c |- - - - - - - - - - - - - - - -| |
  168. PIO1 | (unused) | |
  169. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  170. | direction (11 bit) (rw) | |
  171. + 0x04 |- - - - - - - - - - - - - - - -| |
  172. | data (11 bit) (rw) | /
  173. 0x00920970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1
  174. | edgecapture (4 bit) (rw) | \
  175. + 0x0c |- - - - - - - - - - - - - - - -| |
  176. PIO0 | interruptmask (4 bit) (rw) | |
  177. [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
  178. | (unused) | |
  179. + 0x04 |- - - - - - - - - - - - - - - -| |
  180. | data (4 bit) (ro) | /
  181. 0x00920960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0
  182. | (unused) | \
  183. + 0x1c |- - - - - - - - - - - - - - - -| |
  184. | (unused) | |
  185. + 0x18 |- - - - - - - - - - - - - - - -| |
  186. | snaph (16 bit) (rw) | |
  187. + 0x14 |- - - - - - - - - - - - - - - -| |
  188. TIMER0 | snapl (16 bit) (rw) | |
  189. [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
  190. | periodh (16 bit) (rw) | |
  191. + 0x0c |- - - - - - - - - - - - - - - -| |
  192. | periodl (16 bit) (rw) | |
  193. + 0x08 |- - - - - - - - - - - - - - - -| |
  194. | control (4 bit) (rw) | |
  195. + 0x04 |- - - - - - - - - - - - - - - -| |
  196. | status (2 bit) (rw) | /
  197. 0x00920940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0
  198. | | \
  199. : gap : > (space for UART1)
  200. | | /
  201. 0x00920920 ---32-----------16|15------------0-
  202. | (unused) | \
  203. + 0x1c |- - - - - - - - - - - - - - - -| |
  204. | (unused) | |
  205. + 0x18 |- - - - - - - - - - - - - - - -| |
  206. | (unused) | |
  207. + 0x14 |- - - - - - - - - - - - - - - -| |
  208. UART0 | (unused) | > 0x00000020
  209. [2] + 0x10 |- - - - - - - - - - - - - - - -| |
  210. | control (10 bit) (rw) | |
  211. + 0x0c |- - - - - - - - - - - - - - - -| |
  212. | status (10 bit) (rw) | |
  213. + 0x08 |- - - - - - - - - - - - - - - -| |
  214. | txdata (8 bit) (wo) | |
  215. + 0x04 |- - - - - - - - - - - - - - - -| |
  216. | rxdata (8 bit) (ro) | /
  217. 0x00920900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0
  218. - - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
  219. 0x00920900 -----------------------------------
  220. | | \
  221. : (real size : |
  222. OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE
  223. : unknown) : | = 0x00000100
  224. | | /
  225. 0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE
  226. - - - - - - - - - - - on chip memory - - - - - - - - - - -
  227. 0x00920800 ---32-----------16|15------------0-
  228. | : | \
  229. | : | |
  230. GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE
  231. | : | | = 0x00000800
  232. | : | /
  233. 0x00920000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
  234. 0x00920000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE
  235. - - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
  236. 0x00920000 ---32-----------16|15------------0-
  237. | gap | \
  238. 0x00910310 --+-------------------------------| |
  239. | | |
  240. | register bank (size = 0x10) | |
  241. | +--------.---.---.--- | |
  242. | | bank 0 \ 1 \ 2 \ 3 \ | |
  243. | |---------------------------+ | |
  244. LAN91C111 | | BANK | RESERVED | | |
  245. | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
  246. | | RPCR | MIR | | | = 0x00010000
  247. | |- - - - - - -|- - - - - - -| | |
  248. | | COUNTER | RCR | | |
  249. | |- - - - - - -|- - - - - - -| | |
  250. | | EPH STATUS | TCR | | |
  251. | +---------------------------+ | |
  252. 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
  253. | gap | /
  254. 0x00910000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE
  255. | |
  256. : gap :
  257. : :
  258. - - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
  259. : :
  260. : gap :
  261. | |
  262. 0x00900000 ---32-----------16|15------------0-
  263. 0x00900000 --+32-----------16|15------------0+
  264. | : | \ \
  265. | : | | |
  266. | : | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE
  267. | : | | | = 0x00000100
  268. | : | | /
  269. 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
  270. 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
  271. | : | | \
  272. | : | | |
  273. | : | | > stack area
  274. | : | | |
  275. | : | | V
  276. | : | |
  277. SRAM | : | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
  278. | : | | = 0x00100000
  279. | : | /
  280. 0x00800000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE
  281. 0x00800000 ---8-------------4|3-------------0-
  282. | sector 127 | \
  283. + 0x7f0000 |- - - - - - - - - - - - - - - -| |
  284. | : | |
  285. Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
  286. | sector 1 : | | = 0x00800000
  287. + 0x010000 |- - - - - - - - - - - - - - - -| |
  288. | sector 0 (size = 0x10000) | /
  289. 0x00000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE
  290. ===============================================================================
  291. F L A S H M E M O R Y A L L O C A T I O N
  292. ===============================================================================
  293. 0x00800000 ---8-------------4|3-------------0-
  294. | : | \
  295. SAFE | : | > 1 MByte
  296. FPGA conf. | : | / (NOT usable by software)
  297. 0x00700000 --+- - - - - - - -:- - - - - - - -+-
  298. | : | \
  299. USER | : | > 1 MByte
  300. FPGA conf. | : | / (NOT usable by software)
  301. 0x00600000 --+- - - - - - - -:- - - - - - - -+-
  302. | : | \
  303. | : | |
  304. WEB pages | : | > 2 MByte
  305. | : | | (provisory usable)
  306. | : | /
  307. 0x00400000 --+- - - - - - - -:- - - - - - - -+-
  308. | : | \
  309. | : | |
  310. | : | |
  311. | : | > 4 MByte free for use
  312. | : | |
  313. 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
  314. | : | /
  315. 0x00000000 |- - - - - - - -:- - - - - - - -+- - u-boot environment
  316. 0x00000000 ---8-------------4|3-------------0-
  317. ===============================================================================
  318. R E F E R E N C E S
  319. ===============================================================================
  320. [1] http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf
  321. [2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
  322. [3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
  323. [4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
  324. [5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
  325. http://www.altera.com/literature/wp/wp_epcs_cyc.pdf
  326. [6] http://www.opencores.org/projects/ata/
  327. http://www.t13.org/index.html
  328. ===============================================================================
  329. Stephan Linz <linz@li-pro.net>