README.RPXlite 20 KB

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  1. # Porting U-Boot onto RPXlite board
  2. # Written by Yoo. Jonghoon
  3. # E-Mail : yooth@ipone.co.kr
  4. # IP ONE Inc.
  5. # Since 2001. 1. 29
  6. # Shell : bash
  7. # Cross-compile tools : Montavista Hardhat
  8. # Debugging tools : Windriver VisionProbe (PowerPC BDM)
  9. # ppcboot ver. : ppcboot-0.8.1
  10. ###############################################################
  11. # 1. Hardware setting
  12. ###############################################################
  13. 1.1. Board, BDM settings
  14. Install board, BDM, connect each other
  15. 1.2. Save Register value
  16. Boot with board-on monitor program and save the
  17. register values with BDM.
  18. 1.3. Configure flash programmer
  19. Check flash memory area in the memory map.
  20. 0xFFC00000 - 0xFFFFFFFF
  21. Boot monitor program is at
  22. 0xFFF00000
  23. You can program on-board flash memory with VisionClick
  24. flash programmer. Set the target flash device as:
  25. 29DL800B
  26. (?) The flash memory device in the board *is* 29LV800B,
  27. but I cannot program it with '29LV800B' option.
  28. (in VisionClick flash programming tools)
  29. I don't know why...
  30. 1.4. Save boot monitor program *IMPORTANT*
  31. Upload boot monitor program from board to file.
  32. boot monitor program starts at 0xFFF00000
  33. 1.5. Test flash memory programming
  34. Try to erase boot program in the flash memory,
  35. and re-write them.
  36. *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
  37. BEFORE ERASING FLASH
  38. ###############################################################
  39. # 2. U-Boot setting
  40. ###############################################################
  41. 2.1. Download U-Boot tarball at
  42. ftp://ftp.denx.de
  43. (The latest version is ppcboot-0.8.1.tar.bz2)
  44. To extract the archive use the following syntax :
  45. > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -
  46. 2.2. Add the following lines in '.profile'
  47. export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin
  48. 2.3. Make board specific config, for example:
  49. > cd ppcboot-0.8.1
  50. > make TQM860L_config
  51. Now we can build ppcboot bin files.
  52. After make all, you must see these files in your
  53. ppcboot root directory.
  54. ppcboot
  55. ppcboot.bin
  56. ppcboot.srec
  57. ppcboot.map
  58. 2.4. Make your own board directory into the
  59. ppcboot-0.8.1/board
  60. and make your board-specific files here.
  61. For exmanple, tqm8xx files are composed of
  62. .depend : Nothing
  63. Makefile : To make config file
  64. config.mk : Sets base address
  65. flash.c : Flash memory control files
  66. ppcboot.lds : linker(ld) script? (I don't know this yet)
  67. tqm8xx.c : DRAM control and board check routines
  68. And, add your board config lines in the
  69. ppcboot-0.8.1/Makefile
  70. Finally, add config_(your board).h file in the
  71. ppcboot-0.8.1/include/
  72. I've made board/rpxlite directory, and just copied
  73. tqm8xx settings for now.
  74. Rebuild ppcboot for rpxlite board:
  75. > make rpxlite_config
  76. > make
  77. ###############################################################
  78. # 3. U-Boot porting
  79. ###############################################################
  80. 3.1. My RPXlite files are based on tqm8xx board files.
  81. > cd board
  82. > cp -r tqm8xx RPXLITE
  83. > cd RPXLITE
  84. > mv tqm8xx.c RPXLITE.c
  85. > cd ../../include
  86. > cp config_tqm8xx.h config_RPXLITE.h
  87. 3.2. Modified files are:
  88. board/RPXLITE/RPXLITE.c /* DRAM-related routines */
  89. board/RPXLITE/flash.c /* flash-related routines */
  90. board/RPXLITE/config.mk /* set text base address */
  91. cpu/mpc8xx/serial.c /* board specific register setting */
  92. include/config_RPXLITE.h /* board specific registers */
  93. See 'reg_config.txt' for register values in detail.
  94. ###############################################################
  95. # 4. Running Linux
  96. ###############################################################
  97. ###############################################################
  98. # Misc Information
  99. ###############################################################
  100. mem_config.txt:
  101. ===============
  102. Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
  103. manufacturer id : 01 (AMD)
  104. device id : 5B (AM29LV800B)
  105. size : 4Mbyte
  106. sector # : 19
  107. Sector information :
  108. number start addr. size
  109. 00 FFC0_0000 64
  110. 01 FFC1_0000 32
  111. 02 FFC1_8000 32
  112. 03 FFC2_0000 128
  113. 04 FFC4_0000 256
  114. 05 FFC8_0000 256
  115. 06 FFCC_0000 256
  116. 07 FFD0_0000 256
  117. 08 FFD4_0000 256
  118. 09 FFD8_0000 256
  119. 10 FFDC_0000 256
  120. 11 FFE0_0000 256
  121. 12 FFE4_0000 256
  122. 13 FFE8_0000 256
  123. 14 FFEC_0000 256
  124. 15 FFF0_0000 256
  125. 16 FFF4_0000 256
  126. 17 FFF8_0000 256
  127. 18 FFFC_0000 256
  128. reg_config.txt:
  129. ===============
  130. /*------------------------------------------------------------------- */
  131. /*------------------------------------------------------------------- */
  132. /* SIU (System Interface Unit) */
  133. /* */
  134. /*------------------------------------------------------------------- */
  135. /*------------------------------------------------------------------- */
  136. /*### IMMR */
  137. /*### Internal Memory Map Register */
  138. /*### Chap. 11.4.1 */
  139. ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */
  140. PARTNUM = 0x21
  141. MASKNUM = 0x00
  142. => 0xFA20 2100
  143. ---------------------------------------------------------------------
  144. /*### SIUMCR */
  145. /*### SIU Module Configuration Register */
  146. /*### Chap. 11.4.2 */
  147. /*### Offset : 0x0000 0000 */
  148. EARB = 0
  149. EARP = 0
  150. DSHW = 0
  151. DBGC = 0
  152. DBPC = 0
  153. FRC = 0
  154. DLK = 0
  155. OPAR = 0
  156. PNCS = 0
  157. DPC = 0
  158. MPRE = 0
  159. MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
  160. AEME = 0
  161. SEME = 0
  162. BSC = 0
  163. GB5E = 0
  164. B2DD = 0
  165. B3DD = 0
  166. => 0x0000 0800
  167. ---------------------------------------------------------------------
  168. /*### SYPCR */
  169. /*### System Protection Control Register */
  170. /*### Chap. 11.4.3 */
  171. /*### Offset : 0x0000 0004 */
  172. SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */
  173. BMT = 0x06 /* BUS monitoring timing */
  174. BME = 1 /* BUS monitor enable */
  175. SWF = 1
  176. SWE = 0 /* SW watchdog disable */
  177. SWRI = 0
  178. SWP = 1
  179. => 0xFFFF 0689
  180. ---------------------------------------------------------------------
  181. /*### TESR */
  182. /*### Transfer Error Status Register */
  183. /*### Chap. 11.4.4 */
  184. /*### Offset : 0x0000 0020 */
  185. IEXT = 0
  186. ITMT = 0
  187. IPB = 0000
  188. DEXT = 0
  189. DTMT = 0
  190. DPB = 0000
  191. => 0x0000 0000
  192. ---------------------------------------------------------------------
  193. /*### SIPEND */
  194. /*### SIU Interrupt Pending Register */
  195. /*### Chap. 11.5.4.1 */
  196. /*### Offset : 0x0000 0010 */
  197. IRQ0~IRQ7 = 0
  198. LVL0~LVL7 = 0
  199. => 0x0000 0000
  200. ---------------------------------------------------------------------
  201. /*### SIMASK */
  202. /*### SIU Interrupt Mask Register */
  203. /*### Chap. 11.5.4.2 */
  204. /*### Offset : 0x0000 0014 */
  205. IRM0~IRM7 = 0 /* Mask all interrupts */
  206. LVL0~LVL7 = 0
  207. => 0x0000 0000
  208. ---------------------------------------------------------------------
  209. /*### SIEL */
  210. /*### SIU Interrupt Edge/Level Register */
  211. /*### Chap. 11.5.4.3 */
  212. /*### Offset : 0x0000 0018 */
  213. ED0~ED7 = 0 /* Low level triggered */
  214. WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */
  215. => 0x0000 0000
  216. ---------------------------------------------------------------------
  217. /*### SIVEC */
  218. /*### SIU Interrupt Vector Register */
  219. /*### Chap. 11.5.4.4 */
  220. /*### Offset : 0x0000 001C */
  221. INTC = 3C /* The lowest interrupt is pending..(?) */
  222. => 0x3C00 0000
  223. ---------------------------------------------------------------------
  224. /*### SWSR */
  225. /*### Software Service Register */
  226. /*### Chap. 11.7.1 */
  227. /*### Offset : 0x0000 001E */
  228. SEQ = 0
  229. => 0x0000
  230. ---------------------------------------------------------------------
  231. /*### SDCR */
  232. /*### SDMA Configuration Register */
  233. /*### Chap. 20.2.1 */
  234. /*### Offset : 0x0000 0032 */
  235. FRZ = 0
  236. RAID = 01 /* Priority level 5 (BR5) (normal operation) */
  237. => 0x0000 0001
  238. /*------------------------------------------------------------------- */
  239. /*------------------------------------------------------------------- */
  240. /* UPMA (User Programmable Machine A) */
  241. /* */
  242. /*------------------------------------------------------------------- */
  243. /*------------------------------------------------------------------- */
  244. /*### Chap. 16.6.4.1 */
  245. /*### Offset = 0x0000 017c */
  246. T0 = CFFF CC24 /* Single Read */
  247. T1 = 0FFF CC04
  248. T2 = 0CAF CC04
  249. T3 = 03AF CC08
  250. T4 = 3FBF CC27 /* last */
  251. T5 = FFFF CC25
  252. T6 = FFFF CC25
  253. T7 = FFFF CC25
  254. T8 = CFFF CC24 /* Burst Read */
  255. T9 = 0FFF CC04
  256. T10 = 0CAF CC84
  257. T11 = 03AF CC88
  258. T12 = 3FBF CC27 /* last */
  259. T13 = FFFF CC25
  260. T14 = FFFF CC25
  261. T15 = FFFF CC25
  262. T16 = FFFF CC25
  263. T17 = FFFF CC25
  264. T18 = FFFF CC25
  265. T19 = FFFF CC25
  266. T20 = FFFF CC25
  267. T21 = FFFF CC25
  268. T22 = FFFF CC25
  269. T23 = FFFF CC25
  270. T24 = CFFF CC24 /* Single Write */
  271. T25 = 0FFF CC04
  272. T26 = 0CFF CC04
  273. T27 = 03FF CC00
  274. T28 = 3FFF CC27 /* last */
  275. T29 = FFFF CC25
  276. T30 = FFFF CC25
  277. T31 = FFFF CC25
  278. T32 = CFFF CC24 /* Burst Write */
  279. T33 = 0FFF CC04
  280. T34 = 0CFF CC80
  281. T35 = 03FF CC8C
  282. T36 = 0CFF CC00
  283. T37 = 33FF CC27 /* last */
  284. T38 = FFFF CC25
  285. T39 = FFFF CC25
  286. T40 = FFFF CC25
  287. T41 = FFFF CC25
  288. T42 = FFFF CC25
  289. T43 = FFFF CC25
  290. T44 = FFFF CC25
  291. T45 = FFFF CC25
  292. T46 = FFFF CC25
  293. T47 = FFFF CC25
  294. T48 = C0FF CC24 /* Refresh */
  295. T49 = 03FF CC24
  296. T50 = 0FFF CC24
  297. T51 = 0FFF CC24
  298. T52 = 3FFF CC27 /* last */
  299. T53 = FFFF CC25
  300. T54 = FFFF CC25
  301. T55 = FFFF CC25
  302. T56 = FFFF CC25
  303. T57 = FFFF CC25
  304. T58 = FFFF CC25
  305. T59 = FFFF CC25
  306. T60 = FFFF CC25 /* Exception */
  307. T61 = FFFF CC25
  308. T62 = FFFF CC25
  309. T63 = FFFF CC25
  310. /*------------------------------------------------------------------- */
  311. /*------------------------------------------------------------------- */
  312. /* UPMB */
  313. /* */
  314. /*------------------------------------------------------------------- */
  315. /*------------------------------------------------------------------- */
  316. ---------------------------------------------------------------------
  317. /*### Chap. 16.6.4.1 */
  318. /*------------------------------------------------------------------- */
  319. /*------------------------------------------------------------------- */
  320. /* MEMC */
  321. /* */
  322. /*------------------------------------------------------------------- */
  323. /*------------------------------------------------------------------- */
  324. ---------------------------------------------------------------------
  325. /*### BR0 & OR0 */
  326. /*### Base Registers & Option Registers */
  327. /*### Chap. 16.4.1 & 16.4.2 */
  328. /*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
  329. /*### Flash memory */
  330. BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */
  331. AT = 000
  332. PS = 00
  333. PARE = 0
  334. WP = 0
  335. MS = 0 /* GPCM */
  336. V = 1 /* Valid */
  337. => 0xFE00 0001
  338. AM = 1111 1110 0000 0000 0 /* 32MBytes */
  339. ATM = 000
  340. CSNT/SAM = 0
  341. ACS/G5LA,G5LS = 00
  342. BIH = 1 /* Burst inhibited */
  343. SCY = 0100 /* cycle length = 4 */
  344. SETA = 0
  345. TRLX = 0
  346. EHTR = 0
  347. => 0xFE00 0140
  348. /*### BR1 & OR1 */
  349. /*### Base Registers & Option Registers */
  350. /*### Chap. 16.4.1 & 16.4.2 */
  351. /*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
  352. /*### SDRAM */
  353. BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */
  354. AT = 000
  355. PS = 00
  356. PARE = 0
  357. WP = 0
  358. MS = 1 /* UPMA */
  359. V = 1 /* Valid */
  360. => 0x0000 0081
  361. AM = 1111 1110 0000 0000 /* 32MBytes */
  362. ATM = 000
  363. CSNT/SAM = 1
  364. ACS/G5LA,G5LS = 11
  365. BIH = 0
  366. SCY = 0000 /* cycle length = 0 */
  367. SETA = 0
  368. TRLX = 0
  369. EHTR = 0
  370. => 0xFE00 0E00
  371. /*### BR2 & OR2 */
  372. /*### Base Registers & Option Registers */
  373. /*### Chap. 16.4.1 & 16.4.2 */
  374. /*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */
  375. BR2 & OR2 = 0x0000 0000 /* Not used */
  376. /*### BR3 & OR3 */
  377. /*### Base Registers & Option Registers */
  378. /*### Chap. 16.4.1 & 16.4.2 */
  379. /*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
  380. /*### BCSR */
  381. BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */
  382. AT = 000
  383. PS = 00
  384. PARE = 0
  385. WP = 0
  386. MS = 0 /* GPCM */
  387. V = 1 /* Valid */
  388. => 0xFA40 0001
  389. AM = 1111 1111 0111 1111 1 /* (?) */
  390. ATM = 000
  391. CSNT/SAM = 1
  392. ACS/G5LA,G5LS = 00
  393. BIH = 1 /* Burst inhibited */
  394. SCY = 0001 /* cycle length = 1 */
  395. SETA = 0
  396. TRLX = 0
  397. => 0xFF7F 8910
  398. /*### BR4 & OR4 */
  399. /*### Base Registers & Option Registers */
  400. /*### Chap. 16.4.1 & 16.4.2 */
  401. /*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
  402. /*### NVRAM & SRAM */
  403. BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */
  404. AT = 000
  405. PS = 01
  406. PARE = 0
  407. WP = 0
  408. MS = 0 /* GPCM */
  409. V = 1 /* Valid */
  410. => 0xFA00 0401
  411. AM = 1111 1111 1111 1000 0 /* 8MByte */
  412. ATM = 000
  413. CSNT/SAM = 1
  414. ACS/G5LA,G5LS = 00
  415. BIH = 1 /* Burst inhibited */
  416. SCY = 0111 /* cycle length = 7 */
  417. SETA = 0
  418. TRLX = 0
  419. => 0xFFF8 0970
  420. /*### BR5 & OR5 */
  421. /*### Base Registers & Option Registers */
  422. /*### Chap. 16.4.1 & 16.4.2 */
  423. /*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */
  424. BR5 & OR5 = 0x0000 0000 /* Not used */
  425. /*### BR6 & OR6 */
  426. /*### Base Registers & Option Registers */
  427. /*### Chap. 16.4.1 & 16.4.2 */
  428. /*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */
  429. BR6 & OR6 = 0x0000 0000 /* Not used */
  430. /*### BR7 & OR7 */
  431. /*### Base Registers & Option Registers */
  432. /*### Chap. 16.4.1 & 16.4.2 */
  433. /*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */
  434. BR7 & OR7 = 0x0000 0000 /* Not used */
  435. /*### MAR */
  436. /*### Memory Address Register */
  437. /*### Chap. 16.4.7 */
  438. /*### Offset : 0x0000 0164 */
  439. MA = External memory address
  440. /*### MCR */
  441. /*### Memory Command Register */
  442. /*### Chap. 16.4.5 */
  443. /*### Offset : 0x0000 0168 */
  444. OP = xx /* Command op code */
  445. UM = 1 /* Select UPMA */
  446. MB = 001 /* Select CS1 */
  447. MCLF = xxxx /* Loop times */
  448. MAD = xx xxxx /* Memory array index */
  449. /*### MAMR */
  450. /*### Machine A Mode Register */
  451. /*### Chap. 16.4.4 */
  452. /*### Offset : 0x0000 0170 */
  453. PTA = 0101 1000
  454. PTAE = 1 /* Periodic timer A enabled */
  455. AMA = 010
  456. DSA = 00
  457. G0CLA = 000
  458. GPLA4DIS = 1
  459. RLFA = 0100
  460. WLFA = 0011
  461. TLFA = 0000
  462. => 0x58A0 1430
  463. /*### MBMR */
  464. /*### Machine B Mode Register */
  465. /*### Chap. 16.4.4 */
  466. /*### Offset : 0x0000 0174 */
  467. PTA = 0100 1110
  468. PTAE = 0 /* Periodic timer B disabled */
  469. AMA = 000
  470. DSA = 00
  471. G0CLA = 000
  472. GPLA4DIS = 1
  473. RLFA = 0000
  474. WLFA = 0000
  475. TLFA = 0000
  476. => 0x4E00 1000
  477. /*### MSTAT */
  478. /*### Memory Status Register */
  479. /*### Chap. 16.4.3 */
  480. /*### Offset : 0x0000 0178 */
  481. PER0~PER7 = Parity error
  482. WPER = Write protection error
  483. => 0x0000
  484. /*### MPTPR */
  485. /*### Memory Periodic Timer Prescaler Register */
  486. /*### Chap. 16.4.8 */
  487. /*### Offset : 0x0000 017A */
  488. PTP = 0000 1000 /* Divide by 8 */
  489. => 0x0800
  490. /*### MDR */
  491. /*### Memory Data Register */
  492. /*### Chap. 16.4.6 */
  493. /*### Offset : 0x0000 017C */
  494. MD = Memory data contains the RAM array word
  495. /*------------------------------------------------------------------- */
  496. /*------------------------------------------------------------------- */
  497. /* TIMERS */
  498. /* */
  499. /*------------------------------------------------------------------- */
  500. /*------------------------------------------------------------------- */
  501. ---------------------------------------------------------------------
  502. /*### TBREFx */
  503. /*### Timebase Reference Registers */
  504. /*### Chap. 11.9.2 */
  505. /*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
  506. /*### (Locked) */
  507. TBREFF0 = 0xFFFF FFFF
  508. TBREFF1 = 0xFFFF FFFF
  509. ---------------------------------------------------------------------
  510. /*### TBSCR */
  511. /*### Timebase Status and Control Registers */
  512. /*### Chap. 11.9.3 */
  513. /*### Offset : 0x0000 0200 */
  514. /*### (Locked) */
  515. TBIRQ = 00000000
  516. REF0 = 0
  517. REF1 = 0
  518. REFE0 = 0 /* Reference interrupt disable */
  519. REFE1 = 0
  520. TBF = 1
  521. TBE = 1 /* Timebase enable */
  522. => 0x0003
  523. ---------------------------------------------------------------------
  524. /*### RTCSC */
  525. /*### Real-Time Clock Status and Control Registers */
  526. /*### Chap. 11.10.1 */
  527. /*### Offset : 0x0000 0220 */
  528. /*### (Locked) */
  529. RTCIRQ = 00000000
  530. SEC = 1
  531. ALR = 0
  532. 38K = 0 /* PITRTCLK is driven by 32.768KHz */
  533. SIE = 0
  534. ALE = 0
  535. RTF = 0
  536. RTE = 1 /* Real-Time clock enabled */
  537. => 0x0081
  538. ---------------------------------------------------------------------
  539. /*### RTC */
  540. /*### Real-Time Clock Registers */
  541. /*### Chap. 11.10.2 */
  542. /*### Offset : 0x0000 0224 */
  543. /*### (Locked) */
  544. RTC = Real time clock measured in second
  545. ---------------------------------------------------------------------
  546. /*### RTCAL */
  547. /*### Real-Time Clock Alarm Registers */
  548. /*### Chap. 11.10.3 */
  549. /*### Offset : 0x0000 022C */
  550. /*### (Locked) */
  551. ALARM = 0xFFFF FFFF
  552. ---------------------------------------------------------------------
  553. /*### RTSEC */
  554. /*### Real-Time Clock Alarm Second Registers */
  555. /*### Chap. 11.10.4 */
  556. /*### Offset : 0x0000 0228 */
  557. /*### (Locked) */
  558. COUNTER = Counter bits(fraction of a second)
  559. ---------------------------------------------------------------------
  560. /*### PISCR */
  561. /*### Periodic Interrupt Status and Control Register */
  562. /*### Chap. 11.11.1 */
  563. /*### Offset : 0x0000 0240 */
  564. /*### (Locked) */
  565. PIRQ = 0
  566. PS = 0 /* Write 1 to clear */
  567. PIE = 0
  568. PITF = 1
  569. PTE = 0 /* PIT disabled */
  570. ---------------------------------------------------------------------
  571. /*### PITC */
  572. /*### PIT Count Register */
  573. /*### Chap. 11.11.2 */
  574. /*### Offset : 0x0000 0244 */
  575. /*### (Locked) */
  576. PITC = PIT count
  577. ---------------------------------------------------------------------
  578. /*### PITR */
  579. /*### PIT Register */
  580. /*### Chap. 11.11.3 */
  581. /*### Offset : 0x0000 0248 */
  582. /*### (Locked) */
  583. PIT = PIT count /* Read only */
  584. /*------------------------------------------------------------------- */
  585. /*------------------------------------------------------------------- */
  586. /* CLOCKS */
  587. /* */
  588. /*------------------------------------------------------------------- */
  589. /*------------------------------------------------------------------- */
  590. ---------------------------------------------------------------------
  591. ---------------------------------------------------------------------
  592. /*### SCCR */
  593. /*### System Clock and Reset Control Register */
  594. /*### Chap. 15.6.1 */
  595. /*### Offset : 0x0000 0280 */
  596. /*### (Locked) */
  597. COM = 11 /* Clock output disabled */
  598. TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */
  599. RTDIV = 0 /* The clock is divided by 4 */
  600. RTSEL = 0 /* OSCM(Crystal oscillator) is selected */
  601. CRQEN = 0
  602. PRQEN = 0
  603. EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */
  604. DFSYNC = 00 /* Divided by 1 (normal operation) */
  605. DFBRG = 00 /* Divided by 1 (normal operation) */
  606. DFNL = 000
  607. DFNH = 000
  608. => 0x6200 0000
  609. ---------------------------------------------------------------------
  610. /*### PLPRCR */
  611. /*### PLL, Low-Power, and Reset Control Register */
  612. /*### Chap. 15.6.2 */
  613. /*### Offset : 0x0000 0284 */
  614. /*### (Locked) */
  615. MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */
  616. SPLSS = 0
  617. TEXPS = 0
  618. TMIST = 0
  619. CSRC = 0 /* The general system clock is generated by the DFNH field */
  620. LPM = 00 /* Normal high/normal low mode */
  621. CSR = 0
  622. LOLRE = 0
  623. FIOPD = 0
  624. => 0x0050 0000
  625. ---------------------------------------------------------------------
  626. /*### RSR */
  627. /*### Reset Status Register */
  628. /*### Chap. 12.2 */
  629. /*### Offset : 0x0000 0288 */
  630. /*### (Locked) */
  631. EHRS = External hard reset
  632. ESRS = External soft reset
  633. LLRS = Loss-of-lock reset
  634. SWRS = Software watchdog reset
  635. CSRS = Check stop reset
  636. DBHRS = Debug port hard reset
  637. DBSRS = Debug port soft reset
  638. JTRS = JTAG reset
  639. /*------------------------------------------------------------------- */
  640. /*------------------------------------------------------------------- */
  641. /* DMA */
  642. /* */
  643. /*------------------------------------------------------------------- */
  644. /*------------------------------------------------------------------- */
  645. ---------------------------------------------------------------------
  646. /*### SDSR */
  647. /*### SDMA Status Register */
  648. /*### Chap. 20.2.2 */
  649. /*### Offset : 0x0000 0908 */
  650. SBER = 0 /* SDMA channel bus error */
  651. DSP2 = 0 /* DSP chain2 (Tx) interrupt */
  652. DSP1 = 0 /* DSP chain1 (Rx) interrupt */
  653. => 0x00
  654. /*### SDMR */
  655. /*### SDMA Mask Register */
  656. /*### Chap. 20.2.3 */
  657. /*### Offset : 0x0000 090C */
  658. SBER = 0
  659. DSP2 = 0
  660. DSP1 = 0 /* All interrupts are masked */
  661. => 0x00
  662. /*### SDAR */
  663. /*### SDMA Address Register */
  664. /*### Chap. 20.2.4 */
  665. /*### Offset : 0x0000 0904 */
  666. AR = 0xxxxx xxxx /* current system address */
  667. => 0xFA20 23AC
  668. /*### IDSRx */
  669. /*### IDMA Status Register */
  670. /*### Chap. 20.3.3.2 */
  671. /*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */
  672. AD = 0
  673. DONE = 0
  674. OB = 0
  675. => 0x00
  676. /*### IDMRx */
  677. /*### IDMA Mask Register */
  678. /*### Chap. 20.3.3.3 */
  679. /*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */
  680. AD = 0
  681. DONE = 0
  682. OB = 0