miiphyutil.c 12 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * This provides a bit-banged interface to the ethernet MII management
  25. * channel.
  26. */
  27. #include <common.h>
  28. #include <miiphy.h>
  29. #include <asm/types.h>
  30. #include <linux/list.h>
  31. #include <malloc.h>
  32. #include <net.h>
  33. /* local debug macro */
  34. #undef MII_DEBUG
  35. #undef debug
  36. #ifdef MII_DEBUG
  37. #define debug(fmt,args...) printf (fmt ,##args)
  38. #else
  39. #define debug(fmt,args...)
  40. #endif /* MII_DEBUG */
  41. struct mii_dev {
  42. struct list_head link;
  43. char *name;
  44. int (*read) (char *devname, unsigned char addr,
  45. unsigned char reg, unsigned short *value);
  46. int (*write) (char *devname, unsigned char addr,
  47. unsigned char reg, unsigned short value);
  48. };
  49. static struct list_head mii_devs;
  50. static struct mii_dev *current_mii;
  51. /*****************************************************************************
  52. *
  53. * Initialize global data. Need to be called before any other miiphy routine.
  54. */
  55. void miiphy_init ()
  56. {
  57. INIT_LIST_HEAD (&mii_devs);
  58. current_mii = NULL;
  59. }
  60. /*****************************************************************************
  61. *
  62. * Register read and write MII access routines for the device <name>.
  63. */
  64. void miiphy_register (char *name,
  65. int (*read) (char *devname, unsigned char addr,
  66. unsigned char reg, unsigned short *value),
  67. int (*write) (char *devname, unsigned char addr,
  68. unsigned char reg, unsigned short value))
  69. {
  70. struct list_head *entry;
  71. struct mii_dev *new_dev;
  72. struct mii_dev *miidev;
  73. unsigned int name_len;
  74. /* check if we have unique name */
  75. list_for_each (entry, &mii_devs) {
  76. miidev = list_entry (entry, struct mii_dev, link);
  77. if (strcmp (miidev->name, name) == 0) {
  78. printf ("miiphy_register: non unique device name "
  79. "'%s'\n", name);
  80. return;
  81. }
  82. }
  83. /* allocate memory */
  84. name_len = strlen (name);
  85. new_dev =
  86. (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
  87. if (new_dev == NULL) {
  88. printf ("miiphy_register: cannot allocate memory for '%s'\n",
  89. name);
  90. return;
  91. }
  92. memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
  93. /* initalize mii_dev struct fields */
  94. INIT_LIST_HEAD (&new_dev->link);
  95. new_dev->read = read;
  96. new_dev->write = write;
  97. new_dev->name = (char *)(new_dev + 1);
  98. strncpy (new_dev->name, name, name_len);
  99. new_dev->name[name_len] = '\0';
  100. debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
  101. new_dev->name, new_dev->read, new_dev->write);
  102. /* add it to the list */
  103. list_add_tail (&new_dev->link, &mii_devs);
  104. if (!current_mii)
  105. current_mii = new_dev;
  106. }
  107. int miiphy_set_current_dev (char *devname)
  108. {
  109. struct list_head *entry;
  110. struct mii_dev *dev;
  111. list_for_each (entry, &mii_devs) {
  112. dev = list_entry (entry, struct mii_dev, link);
  113. if (strcmp (devname, dev->name) == 0) {
  114. current_mii = dev;
  115. return 0;
  116. }
  117. }
  118. printf ("No such device: %s\n", devname);
  119. return 1;
  120. }
  121. char *miiphy_get_current_dev ()
  122. {
  123. if (current_mii)
  124. return current_mii->name;
  125. return NULL;
  126. }
  127. /*****************************************************************************
  128. *
  129. * Read to variable <value> from the PHY attached to device <devname>,
  130. * use PHY address <addr> and register <reg>.
  131. *
  132. * Returns:
  133. * 0 on success
  134. */
  135. int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
  136. unsigned short *value)
  137. {
  138. struct list_head *entry;
  139. struct mii_dev *dev;
  140. int found_dev = 0;
  141. int read_ret = 0;
  142. if (!devname) {
  143. printf ("NULL device name!\n");
  144. return 1;
  145. }
  146. list_for_each (entry, &mii_devs) {
  147. dev = list_entry (entry, struct mii_dev, link);
  148. if (strcmp (devname, dev->name) == 0) {
  149. found_dev = 1;
  150. read_ret = dev->read (devname, addr, reg, value);
  151. break;
  152. }
  153. }
  154. if (found_dev == 0)
  155. printf ("No such device: %s\n", devname);
  156. return ((found_dev) ? read_ret : 1);
  157. }
  158. /*****************************************************************************
  159. *
  160. * Write <value> to the PHY attached to device <devname>,
  161. * use PHY address <addr> and register <reg>.
  162. *
  163. * Returns:
  164. * 0 on success
  165. */
  166. int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
  167. unsigned short value)
  168. {
  169. struct list_head *entry;
  170. struct mii_dev *dev;
  171. int found_dev = 0;
  172. int write_ret = 0;
  173. if (!devname) {
  174. printf ("NULL device name!\n");
  175. return 1;
  176. }
  177. list_for_each (entry, &mii_devs) {
  178. dev = list_entry (entry, struct mii_dev, link);
  179. if (strcmp (devname, dev->name) == 0) {
  180. found_dev = 1;
  181. write_ret = dev->write (devname, addr, reg, value);
  182. break;
  183. }
  184. }
  185. if (found_dev == 0)
  186. printf ("No such device: %s\n", devname);
  187. return ((found_dev) ? write_ret : 1);
  188. }
  189. /*****************************************************************************
  190. *
  191. * Print out list of registered MII capable devices.
  192. */
  193. void miiphy_listdev (void)
  194. {
  195. struct list_head *entry;
  196. struct mii_dev *dev;
  197. puts ("MII devices: ");
  198. list_for_each (entry, &mii_devs) {
  199. dev = list_entry (entry, struct mii_dev, link);
  200. printf ("'%s' ", dev->name);
  201. }
  202. puts ("\n");
  203. if (current_mii)
  204. printf ("Current device: '%s'\n", current_mii->name);
  205. }
  206. /*****************************************************************************
  207. *
  208. * Read the OUI, manufacture's model number, and revision number.
  209. *
  210. * OUI: 22 bits (unsigned int)
  211. * Model: 6 bits (unsigned char)
  212. * Revision: 4 bits (unsigned char)
  213. *
  214. * Returns:
  215. * 0 on success
  216. */
  217. int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
  218. unsigned char *model, unsigned char *rev)
  219. {
  220. unsigned int reg = 0;
  221. unsigned short tmp;
  222. if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
  223. debug ("PHY ID register 2 read failed\n");
  224. return (-1);
  225. }
  226. reg = tmp;
  227. debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
  228. if (reg == 0xFFFF) {
  229. /* No physical device present at this address */
  230. return (-1);
  231. }
  232. if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
  233. debug ("PHY ID register 1 read failed\n");
  234. return (-1);
  235. }
  236. reg |= tmp << 16;
  237. debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
  238. *oui = (reg >> 10);
  239. *model = (unsigned char)((reg >> 4) & 0x0000003F);
  240. *rev = (unsigned char)(reg & 0x0000000F);
  241. return (0);
  242. }
  243. /*****************************************************************************
  244. *
  245. * Reset the PHY.
  246. * Returns:
  247. * 0 on success
  248. */
  249. int miiphy_reset (char *devname, unsigned char addr)
  250. {
  251. unsigned short reg;
  252. int loop_cnt;
  253. if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
  254. debug ("PHY status read failed\n");
  255. return (-1);
  256. }
  257. if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) {
  258. debug ("PHY reset failed\n");
  259. return (-1);
  260. }
  261. #ifdef CONFIG_PHY_RESET_DELAY
  262. udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
  263. #endif
  264. /*
  265. * Poll the control register for the reset bit to go to 0 (it is
  266. * auto-clearing). This should happen within 0.5 seconds per the
  267. * IEEE spec.
  268. */
  269. loop_cnt = 0;
  270. reg = 0x8000;
  271. while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
  272. if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
  273. debug ("PHY status read failed\n");
  274. return (-1);
  275. }
  276. }
  277. if ((reg & 0x8000) == 0) {
  278. return (0);
  279. } else {
  280. puts ("PHY reset timed out\n");
  281. return (-1);
  282. }
  283. return (0);
  284. }
  285. /*****************************************************************************
  286. *
  287. * Determine the ethernet speed (10/100/1000). Return 10 on error.
  288. */
  289. int miiphy_speed (char *devname, unsigned char addr)
  290. {
  291. u16 bmcr, anlpar;
  292. #if defined(CONFIG_PHY_GIGE)
  293. u16 btsr;
  294. /*
  295. * Check for 1000BASE-X. If it is supported, then assume that the speed
  296. * is 1000.
  297. */
  298. if (miiphy_is_1000base_x (devname, addr)) {
  299. return _1000BASET;
  300. }
  301. /*
  302. * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
  303. */
  304. /* Check for 1000BASE-T. */
  305. if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
  306. printf ("PHY 1000BT status");
  307. goto miiphy_read_failed;
  308. }
  309. if (btsr != 0xFFFF &&
  310. (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
  311. return _1000BASET;
  312. }
  313. #endif /* CONFIG_PHY_GIGE */
  314. /* Check Basic Management Control Register first. */
  315. if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
  316. printf ("PHY speed");
  317. goto miiphy_read_failed;
  318. }
  319. /* Check if auto-negotiation is on. */
  320. if (bmcr & PHY_BMCR_AUTON) {
  321. /* Get auto-negotiation results. */
  322. if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
  323. printf ("PHY AN speed");
  324. goto miiphy_read_failed;
  325. }
  326. return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
  327. }
  328. /* Get speed from basic control settings. */
  329. return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
  330. miiphy_read_failed:
  331. printf (" read failed, assuming 10BASE-T\n");
  332. return _10BASET;
  333. }
  334. /*****************************************************************************
  335. *
  336. * Determine full/half duplex. Return half on error.
  337. */
  338. int miiphy_duplex (char *devname, unsigned char addr)
  339. {
  340. u16 bmcr, anlpar;
  341. #if defined(CONFIG_PHY_GIGE)
  342. u16 btsr;
  343. /* Check for 1000BASE-X. */
  344. if (miiphy_is_1000base_x (devname, addr)) {
  345. /* 1000BASE-X */
  346. if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
  347. printf ("1000BASE-X PHY AN duplex");
  348. goto miiphy_read_failed;
  349. }
  350. }
  351. /*
  352. * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
  353. */
  354. /* Check for 1000BASE-T. */
  355. if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
  356. printf ("PHY 1000BT status");
  357. goto miiphy_read_failed;
  358. }
  359. if (btsr != 0xFFFF) {
  360. if (btsr & PHY_1000BTSR_1000FD) {
  361. return FULL;
  362. } else if (btsr & PHY_1000BTSR_1000HD) {
  363. return HALF;
  364. }
  365. }
  366. #endif /* CONFIG_PHY_GIGE */
  367. /* Check Basic Management Control Register first. */
  368. if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
  369. puts ("PHY duplex");
  370. goto miiphy_read_failed;
  371. }
  372. /* Check if auto-negotiation is on. */
  373. if (bmcr & PHY_BMCR_AUTON) {
  374. /* Get auto-negotiation results. */
  375. if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
  376. puts ("PHY AN duplex");
  377. goto miiphy_read_failed;
  378. }
  379. return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
  380. FULL : HALF;
  381. }
  382. /* Get speed from basic control settings. */
  383. return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
  384. miiphy_read_failed:
  385. printf (" read failed, assuming half duplex\n");
  386. return HALF;
  387. }
  388. /*****************************************************************************
  389. *
  390. * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
  391. * 1000BASE-T, or on error.
  392. */
  393. int miiphy_is_1000base_x (char *devname, unsigned char addr)
  394. {
  395. #if defined(CONFIG_PHY_GIGE)
  396. u16 exsr;
  397. if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
  398. printf ("PHY extended status read failed, assuming no "
  399. "1000BASE-X\n");
  400. return 0;
  401. }
  402. return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
  403. #else
  404. return 0;
  405. #endif
  406. }
  407. #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  408. /*****************************************************************************
  409. *
  410. * Determine link status
  411. */
  412. int miiphy_link (char *devname, unsigned char addr)
  413. {
  414. unsigned short reg;
  415. /* dummy read; needed to latch some phys */
  416. (void)miiphy_read (devname, addr, PHY_BMSR, &reg);
  417. if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
  418. puts ("PHY_BMSR read failed, assuming no link\n");
  419. return (0);
  420. }
  421. /* Determine if a link is active */
  422. if ((reg & PHY_BMSR_LS) != 0) {
  423. return (1);
  424. } else {
  425. return (0);
  426. }
  427. }
  428. #endif