cmd_pci.c 17 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. /*
  28. * PCI routines
  29. */
  30. #include <common.h>
  31. #include <command.h>
  32. #include <asm/processor.h>
  33. #include <asm/io.h>
  34. #include <pci.h>
  35. unsigned char ShortPCIListing = 1;
  36. /*
  37. * Follows routines for the output of infos about devices on PCI bus.
  38. */
  39. void pci_header_show(pci_dev_t dev);
  40. void pci_header_show_brief(pci_dev_t dev);
  41. /*
  42. * Subroutine: pciinfo
  43. *
  44. * Description: Show information about devices on PCI bus.
  45. * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
  46. * the output will be more or less exhaustive.
  47. *
  48. * Inputs: bus_no the number of the bus to be scanned.
  49. *
  50. * Return: None
  51. *
  52. */
  53. void pciinfo(int BusNum, int ShortPCIListing)
  54. {
  55. int Device;
  56. int Function;
  57. unsigned char HeaderType;
  58. unsigned short VendorID;
  59. pci_dev_t dev;
  60. printf("Scanning PCI devices on bus %d\n", BusNum);
  61. if (ShortPCIListing) {
  62. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  63. printf("_____________________________________________________________\n");
  64. }
  65. for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
  66. HeaderType = 0;
  67. VendorID = 0;
  68. for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
  69. /*
  70. * If this is not a multi-function device, we skip the rest.
  71. */
  72. if (Function && !(HeaderType & 0x80))
  73. break;
  74. dev = PCI_BDF(BusNum, Device, Function);
  75. pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
  76. if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
  77. continue;
  78. if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
  79. if (ShortPCIListing)
  80. {
  81. printf("%02x.%02x.%02x ", BusNum, Device, Function);
  82. pci_header_show_brief(dev);
  83. }
  84. else
  85. {
  86. printf("\nFound PCI device %02x.%02x.%02x:\n",
  87. BusNum, Device, Function);
  88. pci_header_show(dev);
  89. }
  90. }
  91. }
  92. }
  93. static char *pci_classes_str(u8 class)
  94. {
  95. switch (class) {
  96. case PCI_CLASS_NOT_DEFINED:
  97. return "Build before PCI Rev2.0";
  98. break;
  99. case PCI_BASE_CLASS_STORAGE:
  100. return "Mass storage controller";
  101. break;
  102. case PCI_BASE_CLASS_NETWORK:
  103. return "Network controller";
  104. break;
  105. case PCI_BASE_CLASS_DISPLAY:
  106. return "Display controller";
  107. break;
  108. case PCI_BASE_CLASS_MULTIMEDIA:
  109. return "Multimedia device";
  110. break;
  111. case PCI_BASE_CLASS_MEMORY:
  112. return "Memory controller";
  113. break;
  114. case PCI_BASE_CLASS_BRIDGE:
  115. return "Bridge device";
  116. break;
  117. case PCI_BASE_CLASS_COMMUNICATION:
  118. return "Simple comm. controller";
  119. break;
  120. case PCI_BASE_CLASS_SYSTEM:
  121. return "Base system peripheral";
  122. break;
  123. case PCI_BASE_CLASS_INPUT:
  124. return "Input device";
  125. break;
  126. case PCI_BASE_CLASS_DOCKING:
  127. return "Docking station";
  128. break;
  129. case PCI_BASE_CLASS_PROCESSOR:
  130. return "Processor";
  131. break;
  132. case PCI_BASE_CLASS_SERIAL:
  133. return "Serial bus controller";
  134. break;
  135. case PCI_BASE_CLASS_INTELLIGENT:
  136. return "Intelligent controller";
  137. break;
  138. case PCI_BASE_CLASS_SATELLITE:
  139. return "Satellite controller";
  140. break;
  141. case PCI_BASE_CLASS_CRYPT:
  142. return "Cryptographic device";
  143. break;
  144. case PCI_BASE_CLASS_SIGNAL_PROCESSING:
  145. return "DSP";
  146. break;
  147. case PCI_CLASS_OTHERS:
  148. return "Does not fit any class";
  149. break;
  150. default:
  151. return "???";
  152. break;
  153. };
  154. }
  155. /*
  156. * Subroutine: pci_header_show_brief
  157. *
  158. * Description: Reads and prints the header of the
  159. * specified PCI device in short form.
  160. *
  161. * Inputs: dev Bus+Device+Function number
  162. *
  163. * Return: None
  164. *
  165. */
  166. void pci_header_show_brief(pci_dev_t dev)
  167. {
  168. u16 vendor, device;
  169. u8 class, subclass;
  170. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  171. pci_read_config_word(dev, PCI_DEVICE_ID, &device);
  172. pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
  173. pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
  174. printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
  175. vendor, device,
  176. pci_classes_str(class), subclass);
  177. }
  178. /*
  179. * Subroutine: PCI_Header_Show
  180. *
  181. * Description: Reads the header of the specified PCI device.
  182. *
  183. * Inputs: BusDevFunc Bus+Device+Function number
  184. *
  185. * Return: None
  186. *
  187. */
  188. void pci_header_show(pci_dev_t dev)
  189. {
  190. u8 _byte, header_type;
  191. u16 _word;
  192. u32 _dword;
  193. #define PRINT(msg, type, reg) \
  194. pci_read_config_##type(dev, reg, &_##type); \
  195. printf(msg, _##type)
  196. #define PRINT2(msg, type, reg, func) \
  197. pci_read_config_##type(dev, reg, &_##type); \
  198. printf(msg, _##type, func(_##type))
  199. pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
  200. PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
  201. PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
  202. PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
  203. PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
  204. PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
  205. PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
  206. pci_classes_str);
  207. PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
  208. PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
  209. PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
  210. PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
  211. PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
  212. PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
  213. PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
  214. switch (header_type & 0x03) {
  215. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  216. PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
  217. PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
  218. PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
  219. PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
  220. PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
  221. PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
  222. PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
  223. PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
  224. PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
  225. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  226. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  227. PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
  228. PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
  229. break;
  230. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  231. PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
  232. PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
  233. PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
  234. PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
  235. PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
  236. PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
  237. PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
  238. PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
  239. PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
  240. PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
  241. PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
  242. PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
  243. PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
  244. PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
  245. PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
  246. PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
  247. PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
  248. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  249. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  250. PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
  251. break;
  252. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  253. PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
  254. PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
  255. PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
  256. PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
  257. PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
  258. PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
  259. PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
  260. PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
  261. PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
  262. PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
  263. PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
  264. PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
  265. PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
  266. PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
  267. PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
  268. PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
  269. PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
  270. PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
  271. PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  272. PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  273. PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
  274. PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
  275. PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
  276. PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
  277. break;
  278. default:
  279. printf("unknown header\n");
  280. break;
  281. }
  282. #undef PRINT
  283. #undef PRINT2
  284. }
  285. /* Convert the "bus.device.function" identifier into a number.
  286. */
  287. static pci_dev_t get_pci_dev(char* name)
  288. {
  289. char cnum[12];
  290. int len, i, iold, n;
  291. int bdfs[3] = {0,0,0};
  292. len = strlen(name);
  293. if (len > 8)
  294. return -1;
  295. for (i = 0, iold = 0, n = 0; i < len; i++) {
  296. if (name[i] == '.') {
  297. memcpy(cnum, &name[iold], i - iold);
  298. cnum[i - iold] = '\0';
  299. bdfs[n++] = simple_strtoul(cnum, NULL, 16);
  300. iold = i + 1;
  301. }
  302. }
  303. strcpy(cnum, &name[iold]);
  304. if (n == 0)
  305. n = 1;
  306. bdfs[n] = simple_strtoul(cnum, NULL, 16);
  307. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  308. }
  309. static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
  310. {
  311. #define DISP_LINE_LEN 16
  312. ulong i, nbytes, linebytes;
  313. int rc = 0;
  314. if (length == 0)
  315. length = 0x40 / size; /* Standard PCI configuration space */
  316. /* Print the lines.
  317. * once, and all accesses are with the specified bus width.
  318. */
  319. nbytes = length * size;
  320. do {
  321. uint val4;
  322. ushort val2;
  323. u_char val1;
  324. printf("%08lx:", addr);
  325. linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
  326. for (i=0; i<linebytes; i+= size) {
  327. if (size == 4) {
  328. pci_read_config_dword(bdf, addr, &val4);
  329. printf(" %08x", val4);
  330. } else if (size == 2) {
  331. pci_read_config_word(bdf, addr, &val2);
  332. printf(" %04x", val2);
  333. } else {
  334. pci_read_config_byte(bdf, addr, &val1);
  335. printf(" %02x", val1);
  336. }
  337. addr += size;
  338. }
  339. printf("\n");
  340. nbytes -= linebytes;
  341. if (ctrlc()) {
  342. rc = 1;
  343. break;
  344. }
  345. } while (nbytes > 0);
  346. return (rc);
  347. }
  348. static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
  349. {
  350. if (size == 4) {
  351. pci_write_config_dword(bdf, addr, value);
  352. }
  353. else if (size == 2) {
  354. ushort val = value & 0xffff;
  355. pci_write_config_word(bdf, addr, val);
  356. }
  357. else {
  358. u_char val = value & 0xff;
  359. pci_write_config_byte(bdf, addr, val);
  360. }
  361. return 0;
  362. }
  363. static int
  364. pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
  365. {
  366. ulong i;
  367. int nbytes;
  368. extern char console_buffer[];
  369. uint val4;
  370. ushort val2;
  371. u_char val1;
  372. /* Print the address, followed by value. Then accept input for
  373. * the next value. A non-converted value exits.
  374. */
  375. do {
  376. printf("%08lx:", addr);
  377. if (size == 4) {
  378. pci_read_config_dword(bdf, addr, &val4);
  379. printf(" %08x", val4);
  380. }
  381. else if (size == 2) {
  382. pci_read_config_word(bdf, addr, &val2);
  383. printf(" %04x", val2);
  384. }
  385. else {
  386. pci_read_config_byte(bdf, addr, &val1);
  387. printf(" %02x", val1);
  388. }
  389. nbytes = readline (" ? ");
  390. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  391. /* <CR> pressed as only input, don't modify current
  392. * location and move to next. "-" pressed will go back.
  393. */
  394. if (incrflag)
  395. addr += nbytes ? -size : size;
  396. nbytes = 1;
  397. #ifdef CONFIG_BOOT_RETRY_TIME
  398. reset_cmd_timeout(); /* good enough to not time out */
  399. #endif
  400. }
  401. #ifdef CONFIG_BOOT_RETRY_TIME
  402. else if (nbytes == -2) {
  403. break; /* timed out, exit the command */
  404. }
  405. #endif
  406. else {
  407. char *endp;
  408. i = simple_strtoul(console_buffer, &endp, 16);
  409. nbytes = endp - console_buffer;
  410. if (nbytes) {
  411. #ifdef CONFIG_BOOT_RETRY_TIME
  412. /* good enough to not time out
  413. */
  414. reset_cmd_timeout();
  415. #endif
  416. pci_cfg_write (bdf, addr, size, i);
  417. if (incrflag)
  418. addr += size;
  419. }
  420. }
  421. } while (nbytes);
  422. return 0;
  423. }
  424. /* PCI Configuration Space access commands
  425. *
  426. * Syntax:
  427. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  428. * pci next[.b, .w, .l] bus.device.function [addr]
  429. * pci modify[.b, .w, .l] bus.device.function [addr]
  430. * pci write[.b, .w, .l] bus.device.function addr value
  431. */
  432. int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  433. {
  434. ulong addr = 0, value = 0, size = 0;
  435. pci_dev_t bdf = 0;
  436. char cmd = 's';
  437. if (argc > 1)
  438. cmd = argv[1][0];
  439. switch (cmd) {
  440. case 'd': /* display */
  441. case 'n': /* next */
  442. case 'm': /* modify */
  443. case 'w': /* write */
  444. /* Check for a size specification. */
  445. size = cmd_get_data_size(argv[1], 4);
  446. if (argc > 3)
  447. addr = simple_strtoul(argv[3], NULL, 16);
  448. if (argc > 4)
  449. value = simple_strtoul(argv[4], NULL, 16);
  450. case 'h': /* header */
  451. if (argc < 3)
  452. goto usage;
  453. if ((bdf = get_pci_dev(argv[2])) == -1)
  454. return 1;
  455. break;
  456. default: /* scan bus */
  457. value = 1; /* short listing */
  458. bdf = 0; /* bus number */
  459. if (argc > 1) {
  460. if (argv[argc-1][0] == 'l') {
  461. value = 0;
  462. argc--;
  463. }
  464. if (argc > 1)
  465. bdf = simple_strtoul(argv[1], NULL, 16);
  466. }
  467. pciinfo(bdf, value);
  468. return 0;
  469. }
  470. switch (argv[1][0]) {
  471. case 'h': /* header */
  472. pci_header_show(bdf);
  473. return 0;
  474. case 'd': /* display */
  475. return pci_cfg_display(bdf, addr, size, value);
  476. case 'n': /* next */
  477. if (argc < 4)
  478. goto usage;
  479. return pci_cfg_modify(bdf, addr, size, value, 0);
  480. case 'm': /* modify */
  481. if (argc < 4)
  482. goto usage;
  483. return pci_cfg_modify(bdf, addr, size, value, 1);
  484. case 'w': /* write */
  485. if (argc < 5)
  486. goto usage;
  487. return pci_cfg_write(bdf, addr, size, value);
  488. }
  489. return 1;
  490. usage:
  491. cmd_usage(cmdtp);
  492. return 1;
  493. }
  494. /***************************************************/
  495. U_BOOT_CMD(
  496. pci, 5, 1, do_pci,
  497. "list and access PCI Configuration Space",
  498. "[bus] [long]\n"
  499. " - short or long list of PCI devices on bus 'bus'\n"
  500. "pci header b.d.f\n"
  501. " - show header of PCI device 'bus.device.function'\n"
  502. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  503. " - display PCI configuration space (CFG)\n"
  504. "pci next[.b, .w, .l] b.d.f address\n"
  505. " - modify, read and keep CFG address\n"
  506. "pci modify[.b, .w, .l] b.d.f address\n"
  507. " - modify, auto increment CFG address\n"
  508. "pci write[.b, .w, .l] b.d.f address value\n"
  509. " - write to CFG address"
  510. );