mux.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/mux.h>
  11. #include <asm/io.h>
  12. #include "board.h"
  13. /* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
  14. static struct module_pin_mux uart0_pin_mux[] = {
  15. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  16. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  17. {-1},
  18. };
  19. /* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
  20. /* I2C pins C16(scl)/C17(sda) */
  21. static struct module_pin_mux i2c0_pin_mux[] = {
  22. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  23. PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
  24. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  25. PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
  26. {-1},
  27. };
  28. /* MMC0 pins */
  29. static struct module_pin_mux mmc0_pin_mux[] = {
  30. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  31. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  32. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  33. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  34. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  35. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  36. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
  37. {-1},
  38. };
  39. /* MII pins */
  40. static struct module_pin_mux mii1_pin_mux[] = {
  41. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  42. {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  43. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  44. {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  45. {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  46. {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  47. {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  48. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  49. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  50. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  51. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  52. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  53. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  54. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  55. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  56. {-1},
  57. };
  58. /* NAND pins */
  59. static struct module_pin_mux nand_pin_mux[] = {
  60. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  61. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  62. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  63. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  64. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  65. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  66. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  67. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  68. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  69. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  70. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  71. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  72. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  73. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  74. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  75. {-1},
  76. };
  77. void enable_uart0_pin_mux(void)
  78. {
  79. configure_module_pin_mux(uart0_pin_mux);
  80. }
  81. void enable_board_pin_mux()
  82. {
  83. configure_module_pin_mux(i2c0_pin_mux);
  84. configure_module_pin_mux(uart0_pin_mux);
  85. configure_module_pin_mux(mii1_pin_mux);
  86. configure_module_pin_mux(mmc0_pin_mux);
  87. configure_module_pin_mux(nand_pin_mux);
  88. }