board.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Gumstix Pepper and AM335x-based boards
  4. *
  5. * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
  6. * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <errno.h>
  11. #include <init.h>
  12. #include <net.h>
  13. #include <serial.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc_host_def.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/io.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <i2c.h>
  28. #include <miiphy.h>
  29. #include <cpsw.h>
  30. #include <power/tps65217.h>
  31. #include <watchdog.h>
  32. #include "board.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifdef CONFIG_SPL_BUILD
  35. #define OSC (V_OSCK/1000000)
  36. static const struct ddr_data ddr3_data = {
  37. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  38. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  39. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  40. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  41. };
  42. static const struct cmd_control ddr3_cmd_ctrl_data = {
  43. .cmd0csratio = MT41K256M16HA125E_RATIO,
  44. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  45. .cmd1csratio = MT41K256M16HA125E_RATIO,
  46. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  47. .cmd2csratio = MT41K256M16HA125E_RATIO,
  48. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  49. };
  50. static struct emif_regs ddr3_emif_reg_data = {
  51. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  52. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  53. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  54. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  55. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  56. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  57. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  58. };
  59. const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  60. const struct ctrl_ioregs ioregs_ddr3 = {
  61. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  62. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  63. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  64. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  65. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  66. };
  67. static const struct ddr_data ddr2_data = {
  68. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  69. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  70. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  71. };
  72. static const struct cmd_control ddr2_cmd_ctrl_data = {
  73. .cmd0csratio = MT47H128M16RT25E_RATIO,
  74. .cmd1csratio = MT47H128M16RT25E_RATIO,
  75. .cmd2csratio = MT47H128M16RT25E_RATIO,
  76. };
  77. static const struct emif_regs ddr2_emif_reg_data = {
  78. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  79. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  80. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  81. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  82. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  83. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  84. };
  85. const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
  86. const struct ctrl_ioregs ioregs_ddr2 = {
  87. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  88. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  89. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  90. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  91. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  92. };
  93. static int read_eeprom(struct pepper_board_id *header)
  94. {
  95. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  96. return -ENODEV;
  97. }
  98. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  99. sizeof(struct pepper_board_id))) {
  100. return -EIO;
  101. }
  102. return 0;
  103. }
  104. const struct dpll_params *get_dpll_ddr_params(void)
  105. {
  106. struct pepper_board_id header;
  107. enable_i2c0_pin_mux();
  108. i2c_set_bus_num(0);
  109. if (read_eeprom(&header) < 0)
  110. return &dpll_ddr3;
  111. switch (header.device_vendor) {
  112. case GUMSTIX_PEPPER:
  113. return &dpll_ddr2;
  114. case GUMSTIX_PEPPER_DVI:
  115. return &dpll_ddr3;
  116. default:
  117. return &dpll_ddr3;
  118. }
  119. }
  120. void sdram_init(void)
  121. {
  122. const struct dpll_params *dpll = get_dpll_ddr_params();
  123. /*
  124. * Here we are assuming PLL clock reveals the type of RAM.
  125. * DDR2 = 266
  126. * DDR3 = 400
  127. * Note that DDR3 is the default.
  128. */
  129. if (dpll->m == 266) {
  130. config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
  131. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  132. }
  133. else if (dpll->m == 400) {
  134. config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
  135. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  136. }
  137. }
  138. #ifdef CONFIG_SPL_OS_BOOT
  139. int spl_start_uboot(void)
  140. {
  141. /* break into full u-boot on 'c' */
  142. return serial_tstc() && serial_getc() == 'c';
  143. }
  144. #endif
  145. void set_uart_mux_conf(void)
  146. {
  147. enable_uart0_pin_mux();
  148. }
  149. void set_mux_conf_regs(void)
  150. {
  151. enable_board_pin_mux();
  152. }
  153. #endif
  154. int board_init(void)
  155. {
  156. #if defined(CONFIG_HW_WATCHDOG)
  157. hw_watchdog_init();
  158. #endif
  159. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  160. gpmc_init();
  161. return 0;
  162. }
  163. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  164. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  165. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  166. static void cpsw_control(int enabled)
  167. {
  168. /* VTP can be added here */
  169. return;
  170. }
  171. static struct cpsw_slave_data cpsw_slaves[] = {
  172. {
  173. .slave_reg_ofs = 0x208,
  174. .sliver_reg_ofs = 0xd80,
  175. .phy_addr = 0,
  176. .phy_if = PHY_INTERFACE_MODE_RGMII,
  177. },
  178. };
  179. static struct cpsw_platform_data cpsw_data = {
  180. .mdio_base = CPSW_MDIO_BASE,
  181. .cpsw_base = CPSW_BASE,
  182. .mdio_div = 0xff,
  183. .channels = 8,
  184. .cpdma_reg_ofs = 0x800,
  185. .slaves = 1,
  186. .slave_data = cpsw_slaves,
  187. .ale_reg_ofs = 0xd00,
  188. .ale_entries = 1024,
  189. .host_port_reg_ofs = 0x108,
  190. .hw_stats_reg_ofs = 0x900,
  191. .bd_ram_ofs = 0x2000,
  192. .mac_control = (1 << 5),
  193. .control = cpsw_control,
  194. .host_port_num = 0,
  195. .version = CPSW_CTRL_VERSION_2,
  196. };
  197. int board_eth_init(bd_t *bis)
  198. {
  199. int rv, n = 0;
  200. uint8_t mac_addr[6];
  201. uint32_t mac_hi, mac_lo;
  202. const char *devname;
  203. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  204. /* try reading mac address from efuse */
  205. mac_lo = readl(&cdev->macid0l);
  206. mac_hi = readl(&cdev->macid0h);
  207. mac_addr[0] = mac_hi & 0xFF;
  208. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  209. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  210. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  211. mac_addr[4] = mac_lo & 0xFF;
  212. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  213. if (is_valid_ethaddr(mac_addr))
  214. eth_env_set_enetaddr("ethaddr", mac_addr);
  215. }
  216. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  217. rv = cpsw_register(&cpsw_data);
  218. if (rv < 0)
  219. printf("Error %d registering CPSW switch\n", rv);
  220. else
  221. n += rv;
  222. /*
  223. *
  224. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  225. * operating points. So we must set the TX clock delay feature
  226. * in the KSZ9021 PHY. Since we only support a single ethernet
  227. * device in U-Boot, we only do this for the current instance.
  228. */
  229. devname = miiphy_get_current_dev();
  230. /* max rx/tx clock delay, min rx/tx control delay */
  231. miiphy_write(devname, 0x0, 0x0b, 0x8104);
  232. miiphy_write(devname, 0x0, 0xc, 0xa0a0);
  233. /* min rx data delay */
  234. miiphy_write(devname, 0x0, 0x0b, 0x8105);
  235. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  236. /* min tx data delay */
  237. miiphy_write(devname, 0x0, 0x0b, 0x8106);
  238. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  239. return n;
  240. }
  241. #endif