lowlevel_init.S 2.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
  4. */
  5. #include <config.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/macro.h>
  8. .globl lowlevel_init
  9. lowlevel_init:
  10. /* Also setup the Peripheral Port Remap register inside the core */
  11. ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
  12. mcr p15, 0, r0, c15, c2, 4
  13. write32 IPU_CONF, IPU_CONF_DI_EN
  14. write32 CCM_CCMR, CCM_CCMR_SETUP
  15. wait_timer 0x40000
  16. write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
  17. write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
  18. /* Set up clock to 532MHz */
  19. write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
  20. write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
  21. write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
  22. /* Set up MX31 DDR pins */
  23. write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
  24. write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
  25. write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
  26. write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
  27. write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
  28. write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
  29. write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
  30. write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
  31. write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
  32. write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
  33. write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
  34. write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
  35. write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
  36. write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
  37. write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
  38. write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
  39. write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
  40. write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
  41. write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
  42. write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
  43. write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
  44. write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
  45. write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
  46. write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
  47. write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
  48. write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
  49. write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
  50. /* Set up MX31 DDR Memory Controller */
  51. write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
  52. write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
  53. /* Perform DDR init sequence */
  54. write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
  55. write32 CSD0_BASE | 0x0f00, 0x12344321
  56. write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
  57. write32 CSD0_BASE, 0x12344321
  58. write32 CSD0_BASE, 0x12344321
  59. write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
  60. write8 CSD0_BASE | 0x00000033, 0xda
  61. write8 CSD0_BASE | 0x01000000, 0xff
  62. write32 WEIM_ESDCTL0, ESDCTL_RW
  63. write32 CSD0_BASE, 0xDEADBEEF
  64. write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
  65. mov pc, lr