cm_t35.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
  4. *
  5. * Authors: Mike Rapoport <mike@compulab.co.il>
  6. * Igor Grinberg <grinberg@compulab.co.il>
  7. *
  8. * Derived from omap3evm and Beagle Board by
  9. * Manikandan Pillai <mani.pillai@ti.com>
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <x0khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <env.h>
  15. #include <init.h>
  16. #include <status_led.h>
  17. #include <netdev.h>
  18. #include <net.h>
  19. #include <i2c.h>
  20. #include <usb.h>
  21. #include <mmc.h>
  22. #include <splash.h>
  23. #include <twl4030.h>
  24. #include <linux/compiler.h>
  25. #include <linux/delay.h>
  26. #include <asm/io.h>
  27. #include <linux/errno.h>
  28. #include <asm/arch/mem.h>
  29. #include <asm/arch/mux.h>
  30. #include <asm/arch/mmc_host_def.h>
  31. #include <asm/arch/sys_proto.h>
  32. #include <asm/mach-types.h>
  33. #include <asm/ehci-omap.h>
  34. #include <asm/gpio.h>
  35. #include "../common/common.h"
  36. #include "../common/eeprom.h"
  37. DECLARE_GLOBAL_DATA_PTR;
  38. const omap3_sysinfo sysinfo = {
  39. DDR_DISCRETE,
  40. "CM-T3x board",
  41. "NAND",
  42. };
  43. #ifdef CONFIG_SPL_BUILD
  44. /*
  45. * Routine: get_board_mem_timings
  46. * Description: If we use SPL then there is no x-loader nor config header
  47. * so we have to setup the DDR timings ourself on both banks.
  48. */
  49. void get_board_mem_timings(struct board_sdrc_timings *timings)
  50. {
  51. timings->mr = MICRON_V_MR_165;
  52. timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
  53. timings->ctrla = MICRON_V_ACTIMA_165;
  54. timings->ctrlb = MICRON_V_ACTIMB_165;
  55. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  56. }
  57. #endif
  58. struct splash_location splash_locations[] = {
  59. {
  60. .name = "nand",
  61. .storage = SPLASH_STORAGE_NAND,
  62. .flags = SPLASH_STORAGE_RAW,
  63. .offset = 0x100000,
  64. },
  65. };
  66. int splash_screen_prepare(void)
  67. {
  68. return splash_source_load(splash_locations,
  69. ARRAY_SIZE(splash_locations));
  70. }
  71. /*
  72. * Routine: board_init
  73. * Description: hardware init.
  74. */
  75. int board_init(void)
  76. {
  77. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  78. /* board id for Linux */
  79. if (get_cpu_family() == CPU_OMAP34XX)
  80. gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
  81. else
  82. gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
  83. /* boot param addr */
  84. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  85. #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  86. status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
  87. #endif
  88. return 0;
  89. }
  90. /*
  91. * Routine: get_board_rev
  92. * Description: read system revision
  93. */
  94. u32 get_board_rev(void)
  95. {
  96. return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
  97. };
  98. int misc_init_r(void)
  99. {
  100. cl_print_pcb_info();
  101. omap_die_id_display();
  102. return 0;
  103. }
  104. /*
  105. * Routine: set_muxconf_regs
  106. * Description: Setting up the configuration Mux registers specific to the
  107. * hardware. Many pins need to be moved from protect to primary
  108. * mode.
  109. */
  110. static void cm_t3x_set_common_muxconf(void)
  111. {
  112. /* SDRC */
  113. MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
  114. MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
  115. MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
  116. MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
  117. MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
  118. MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
  119. MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
  120. MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
  121. MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
  122. MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
  123. MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
  124. MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
  125. MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
  126. MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
  127. MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
  128. MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
  129. MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
  130. MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
  131. MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
  132. MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
  133. MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
  134. MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
  135. MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
  136. MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
  137. MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
  138. MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
  139. MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
  140. MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
  141. MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
  142. MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
  143. MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
  144. MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
  145. MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
  146. MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
  147. MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
  148. MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
  149. MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
  150. MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
  151. MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
  152. /* GPMC */
  153. MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
  154. MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
  155. MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
  156. MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
  157. MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
  158. MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
  159. MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
  160. MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
  161. MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
  162. MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
  163. MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
  164. MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
  165. MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
  166. MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
  167. MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
  168. MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
  169. MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
  170. MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
  171. MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
  172. MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
  173. MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
  174. MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
  175. MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
  176. MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
  177. MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
  178. MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
  179. MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
  180. /* SB-T35 Ethernet */
  181. MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
  182. /* DVI enable */
  183. MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
  184. /* DataImage backlight */
  185. MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
  186. /* CM-T3x Ethernet */
  187. MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
  188. MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
  189. MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
  190. MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
  191. MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
  192. MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
  193. MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
  194. MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
  195. MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
  196. /* DSS */
  197. MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
  198. MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
  199. MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
  200. MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
  201. MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
  202. MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
  203. MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
  204. MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
  205. MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
  206. MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
  207. MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
  208. MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
  209. MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
  210. MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
  211. MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
  212. MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
  213. /* serial interface */
  214. MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
  215. MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
  216. /* mUSB */
  217. MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
  218. MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
  219. MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
  220. MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
  221. MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
  222. MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
  223. MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
  224. MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
  225. MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
  226. MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
  227. MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
  228. MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
  229. /* USB EHCI */
  230. MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
  231. MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
  232. MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
  233. MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
  234. MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
  235. MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
  236. MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
  237. MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
  238. MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
  239. MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
  240. MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
  241. MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
  242. MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
  243. MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
  244. MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
  245. MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
  246. MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
  247. MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
  248. MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
  249. MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
  250. MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
  251. MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
  252. MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
  253. MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
  254. /* SB_T35_USB_HUB_RESET_GPIO */
  255. MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
  256. /* I2C1 */
  257. MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
  258. MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
  259. /* I2C2 */
  260. MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
  261. MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
  262. /* I2C3 */
  263. MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
  264. MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
  265. /* control and debug */
  266. MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
  267. MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
  268. MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
  269. MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
  270. MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
  271. MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
  272. MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
  273. MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
  274. MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
  275. MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
  276. /* MMC1 */
  277. MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
  278. MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
  279. MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
  280. MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
  281. MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
  282. MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
  283. /* SPI */
  284. MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
  285. MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
  286. MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
  287. MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
  288. /* display controls */
  289. MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
  290. }
  291. static void cm_t35_set_muxconf(void)
  292. {
  293. /* DSS */
  294. MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
  295. MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
  296. MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
  297. MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
  298. MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
  299. MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
  300. MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
  301. MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
  302. MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
  303. MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
  304. MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
  305. MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
  306. /* MMC1 */
  307. MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
  308. MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
  309. MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
  310. MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
  311. }
  312. static void cm_t3730_set_muxconf(void)
  313. {
  314. /* DSS */
  315. MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
  316. MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
  317. MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
  318. MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
  319. MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
  320. MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
  321. MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
  322. MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
  323. MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
  324. MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
  325. MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
  326. MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
  327. }
  328. void set_muxconf_regs(void)
  329. {
  330. cm_t3x_set_common_muxconf();
  331. if (get_cpu_family() == CPU_OMAP34XX)
  332. cm_t35_set_muxconf();
  333. else
  334. cm_t3730_set_muxconf();
  335. }
  336. #if defined(CONFIG_MMC)
  337. #define SB_T35_WP_GPIO 59
  338. int board_mmc_getcd(struct mmc *mmc)
  339. {
  340. u8 val;
  341. if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
  342. return -1;
  343. return !(val & 1);
  344. }
  345. int board_mmc_init(bd_t *bis)
  346. {
  347. return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
  348. }
  349. #endif
  350. #if defined(CONFIG_MMC)
  351. void board_mmc_power_init(void)
  352. {
  353. twl4030_power_mmc_init(0);
  354. }
  355. #endif
  356. #ifdef CONFIG_SYS_I2C_OMAP24XX
  357. /*
  358. * Routine: reset_net_chip
  359. * Description: reset the Ethernet controller via TPS65930 GPIO
  360. */
  361. static int cm_t3x_reset_net_chip(int gpio)
  362. {
  363. /* Set GPIO1 of TPS65930 as output */
  364. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
  365. 0x02);
  366. /* Send a pulse on the GPIO pin */
  367. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
  368. 0x02);
  369. udelay(1);
  370. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
  371. 0x02);
  372. mdelay(40);
  373. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
  374. 0x02);
  375. mdelay(1);
  376. return 0;
  377. }
  378. #else
  379. static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
  380. #endif
  381. #ifdef CONFIG_SMC911X
  382. /*
  383. * Routine: handle_mac_address
  384. * Description: prepare MAC address for on-board Ethernet.
  385. */
  386. static int handle_mac_address(void)
  387. {
  388. unsigned char enetaddr[6];
  389. int rc;
  390. rc = eth_env_get_enetaddr("ethaddr", enetaddr);
  391. if (rc)
  392. return 0;
  393. rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
  394. if (rc)
  395. return rc;
  396. if (!is_valid_ethaddr(enetaddr))
  397. return -1;
  398. return eth_env_set_enetaddr("ethaddr", enetaddr);
  399. }
  400. /*
  401. * Routine: board_eth_init
  402. * Description: initialize module and base-board Ethernet chips
  403. */
  404. #define SB_T35_SMC911X_BASE (CONFIG_SMC911X_BASE + SZ_16M)
  405. int board_eth_init(bd_t *bis)
  406. {
  407. int rc = 0, rc1 = 0;
  408. rc1 = handle_mac_address();
  409. if (rc1)
  410. printf("No MAC address found! ");
  411. rc1 = cl_omap3_smc911x_init(0, 5, CONFIG_SMC911X_BASE,
  412. cm_t3x_reset_net_chip, -EINVAL);
  413. if (rc1 > 0)
  414. rc++;
  415. rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
  416. if (rc1 > 0)
  417. rc++;
  418. return rc;
  419. }
  420. #endif
  421. #ifdef CONFIG_USB_EHCI_OMAP
  422. struct omap_usbhs_board_data usbhs_bdata = {
  423. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  424. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  425. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  426. };
  427. #define SB_T35_USB_HUB_RESET_GPIO 167
  428. int ehci_hcd_init(int index, enum usb_init_type init,
  429. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  430. {
  431. u8 val;
  432. int offset;
  433. cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
  434. offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
  435. twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
  436. /* Set GPIO6 and GPIO7 of TPS65930 as output */
  437. val |= 0xC0;
  438. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
  439. offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
  440. /* Take both PHYs out of reset */
  441. twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
  442. udelay(1);
  443. return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
  444. }
  445. int ehci_hcd_stop(void)
  446. {
  447. cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
  448. return omap_ehci_hcd_stop();
  449. }
  450. #endif /* CONFIG_USB_EHCI_OMAP */