README.ppc440 8.2 KB

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  1. PowerPC 440
  2. Last Update: September 11, 2002
  3. =======================================================================
  4. OVERVIEW
  5. ============
  6. Support for the ppc440 is contained in the cpu/ppc44x directory
  7. and enabled via the CONFIG_440 flag. It is largely based on the
  8. 405gp code. A sample board support implementation is contained
  9. in the board/ebony directory.
  10. All testing was performed using the AMCC Ebony board using both
  11. Rev B and Rev C silicon. However, since the Rev B. silicon has
  12. extensive errata, support for Rev B. is minimal (it boots, and
  13. features such as i2c, pci, tftpboot, etc. seem to work ok).
  14. The expectation is that all new board designs will be using
  15. Rev C or later parts -- if not, you may be in for a rough ride ;-)
  16. The ppc440 port does a fair job of keeping "board-specific" code
  17. out of the "cpu-specific" source. The goal of course was to
  18. provide mechanisms for each board to customize without having
  19. to clutter the cpu-specific source with a lot of ifdefs. Most
  20. of these mechanisms are described in the following sections.
  21. MEMORY MANAGEMENT
  22. =================
  23. The ppc440 doesn't run in "real mode". The MMU must be active
  24. at all times. Additionally, the 440 implements a 36-bit physical
  25. memory space that gets mapped into the PowerPC 32-bit virtual
  26. address space. So things like memory-mapped peripherals, etc must
  27. all be mapped in. Once this is done, the 32-bit virtual address
  28. space is then viewed as though it were physical memory.
  29. However, this means that memory, peripherals, etc can be configured
  30. to appear (mostly) anywhere in the virtual address space. Each board
  31. must define its own mappings using the tlbtab (see board/ebony/init.S).
  32. The actual TLB setup is performed by the cpu-specific code.
  33. Although each board is free to define its own mappings, there are
  34. several definitions to be aware of. These definitions may be used in
  35. the cpu-specific code (vs. board-specific code), so you should
  36. at least review these before deciding to make any changes ... it
  37. will probably save you some headaches ;-)
  38. CONFIG_SYS_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
  39. CONFIG_SYS_FLASH_BASE - The virtual address where FLASH is mapped.
  40. CONFIG_SYS_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
  41. This mapping provides access to PCI-bus memory.
  42. CONFIG_SYS_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
  43. peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
  44. CONFIG_SYS_ISRAM_BASE - The virtual address where the 440 internal SRAM is
  45. mapped. The internal SRAM is equivalent to 405gp OCM and is used
  46. for the initial stack.
  47. CONFIG_SYS_PCI_BASE - The virtual address where the 440 PCI-x bridge config
  48. registers are mapped.
  49. CONFIG_SYS_PCI_TARGBASE - The PCI address that is mapped to the virtual address
  50. defined by CONFIG_SYS_PCI_MEMBASE.
  51. UART / SERIAL
  52. =================
  53. The UART port works fine when an external serial clock is provided
  54. (like the one on the Ebony board) and when using internal clocking.
  55. This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using
  56. internal clocking, the "ideal baud rate" settings in the 440GP
  57. user manual are automatically calculated.
  58. I2C
  59. =================
  60. The i2c utilities have been tested on both Rev B. and Rev C. and
  61. look good. The 'i2c probe' command implementation has been updated to
  62. allow for 'skipped' addresses. Some i2c slaves are write only and
  63. cause problems when a probe (read) is performed (for example the
  64. CDCV850 clock controller at address 0x69 on the ebony board).
  65. To prevent probing certain addresses you can define the
  66. CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When
  67. defined, all specified addresses are skipped during a probe.
  68. The addresses that are skipped will be displayed in the output
  69. of the 'i2c probe' command.
  70. For example, to prevent probing address 0x69, define the macro as
  71. follows:
  72. #define CONFIG_SYS_I2C_NOPROBES {0x69}
  73. Similarly, to prevent probing addresses 0x69 and 0x70, define the
  74. macro a:
  75. #define CONFIG_SYS_I2C_NOPROBES {0x69, 0x70}
  76. DDR SDRAM CONTROLLER
  77. ====================
  78. SDRAM controller intialization using Serial Presence Detect (SPD) is
  79. now supported (thanks Jun). It is enabled by defining CONFIG_SPD_EEPROM.
  80. The i2c eeprom addresses are controlled by the SPD_EEPROM_ADDRESS macro.
  81. NOTE: The SPD_EEPROM_ADDRESS macro is defined differently than for other
  82. processors. Traditionally, it defined a single address. For the 440 it
  83. defines an array of addresses to support multiple banks. Address order
  84. is significant: the addresses are used in order to program the BankN
  85. registers. For example, two banks with i2c addresses of 0x53 (bank 0)
  86. and 0x52 (bank 1) would be defined as follows:
  87. #define SPD_EEPROM_ADDRESS {0x53,0x52}
  88. PCI-X BRIDGE
  89. ====================
  90. PCI is an area that requires lots of flexibility since every board has
  91. its own set of constraints and configuration. This section describes the
  92. 440 implementation.
  93. CPC0_STRP1[PISE] -- if the PISE strap bit is not asserted, PCI init
  94. is aborted and an indication is printed. This is NOT considered an
  95. error -- only an indication that PCI shouldn't be initialized. This
  96. gives you a chance to edit the i2c bootstrap eeproms using the i2c
  97. utilities once you get to the U-Boot command prompt. NOTE: the default
  98. 440 bootstrap options (not using i2c eeprom) negates this bit.
  99. The cpu-specific code sets up a default pci_controller structure
  100. that maps in a single PCI I/O space and PCI memory space. The I/O
  101. space begins at PCI I/O address 0 and the PCI memory space is
  102. 256 MB starting at PCI address CONFIG_SYS_PCI_TARGBASE. After the
  103. pci_controller structure is initialized, the cpu-specific code will
  104. call the routine pci_pre_init(). This routine is implemented by
  105. board-specific code & is where the board can over-ride/extend the
  106. default pci_controller structure settings and exspecially provide
  107. a routine to map the PCI interrupts and do other pre-initialization
  108. tasks. If pci_pre_init() returns a value of zero, PCI initialization
  109. is aborted; otherwise the controller structure is registered and
  110. initialization continues.
  111. The default 440GP PCI target configuration is minimal -- it assumes that
  112. the strapping registers are set as necessary. Since the strapping bits
  113. provide very limited flexibility, you may want to customize the boards
  114. target configuration. If CONFIG_SYS_PCI_TARGET_INIT is defined, the cpu-specific
  115. code will call the routine pci_target_init() which you must implement
  116. in your board-specific code.
  117. Target initialization is completed by the cpu-specific code by
  118. initializing the subsystem id and subsystem vendor id, and then ensuring
  119. that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
  120. The default PCI master initialization maps in 256 MB of pci memory
  121. starting at PCI address CONFIG_SYS_PCI_MEMBASE. To customize this, define
  122. PCI_MASTER_INIT. This will call the routine pci_master_init() in your
  123. board-specific code rather than performing the default master
  124. initialization.
  125. The decision to perform PCI host configuration must often be determined
  126. at run time. The ppc440 port differs from most other implementations in
  127. that it requires the board to determine its host configuration at run
  128. time rather than by using compile-time flags. This shouldn't create a
  129. large impact on the board-specific code since the board only needs to
  130. implement a single routine that returns a zero or non-zero value:
  131. is_pci_host().
  132. Justification for this becomes clear when considering systems running
  133. in a cPCI environment:
  134. 1. Arbiter strapping: Many cPCI boards provide an external arbiter (often
  135. part of the PCI-to-PCI bridge). Even though the arbiter is external (the
  136. arbiter strapping is negated), the CPU may still be required to perform
  137. local PCI bus configuration.
  138. 2. Host only: PPMC boards must sample the MONARCH# signal at run-time.
  139. Depending on the configuration of the carrier boar, the PPMC board must
  140. determine if it should configure the PCI bus at run-time. And in most
  141. cases, access to the MONARCH# signal is board-specific (e.g. via
  142. board-specific FPGA registers, etc).
  143. In any event, the is_pci_host() routine gives each board the opportunity
  144. to decide at run-time. If your board is always configured a certain way,
  145. then just hardcode a return of 1 or 0 as appropriate.
  146. Regards,
  147. --Scott
  148. <smcnutt@artesyncp.com>