README.fsl-ddr 9.4 KB

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  1. Table of interleaving modes supported in cpu/8xxx/ddr/
  2. ======================================================
  3. +-------------+---------------------------------------------------------+
  4. | | Rank Interleaving |
  5. | +--------+-----------+-----------+------------+-----------+
  6. |Memory | | | | 2x2 | 4x1 |
  7. |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  8. |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
  9. +-------------+--------+-----------+-----------+------------+-----------+
  10. |None | Yes | Yes | Yes | Yes | Yes |
  11. +-------------+--------+-----------+-----------+------------+-----------+
  12. |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
  13. | |CS0 Only| | | {CS0+CS1} | |
  14. +-------------+--------+-----------+-----------+------------+-----------+
  15. |Page | Yes | Yes | No | No, Only(*)| Yes |
  16. | |CS0 Only| | | {CS0+CS1} | |
  17. +-------------+--------+-----------+-----------+------------+-----------+
  18. |Bank | Yes | Yes | No | No, Only(*)| Yes |
  19. | |CS0 Only| | | {CS0+CS1} | |
  20. +-------------+--------+-----------+-----------+------------+-----------+
  21. |Superbank | No | Yes | No | No, Only(*)| Yes |
  22. | | | | | {CS0+CS1} | |
  23. +-------------+--------+-----------+-----------+------------+-----------+
  24. (*) Although the hardware can be configured with memory controller
  25. interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
  26. from each controller. {CS2+CS3} on each controller are only rank
  27. interleaved on that controller.
  28. For memory controller interleaving, identical DIMMs are suggested. Software
  29. doesn't check the size or organization of interleaved DIMMs.
  30. The ways to configure the ddr interleaving mode
  31. ==============================================
  32. 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
  33. under "CONFIG_EXTRA_ENV_SETTINGS", like:
  34. #define CONFIG_EXTRA_ENV_SETTINGS \
  35. "hwconfig=fsl_ddr:ctlr_intlv=bank" \
  36. ......
  37. 2. Run u-boot "setenv" command to configure the memory interleaving mode.
  38. Either numerical or string value is accepted.
  39. # disable memory controller interleaving
  40. setenv hwconfig "fsl_ddr:ctlr_intlv=null"
  41. # cacheline interleaving
  42. setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
  43. # page interleaving
  44. setenv hwconfig "fsl_ddr:ctlr_intlv=page"
  45. # bank interleaving
  46. setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
  47. # superbank
  48. setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
  49. # disable bank (chip-select) interleaving
  50. setenv hwconfig "fsl_ddr:bank_intlv=null"
  51. # bank(chip-select) interleaving cs0+cs1
  52. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
  53. # bank(chip-select) interleaving cs2+cs3
  54. setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
  55. # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
  56. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
  57. # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
  58. setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
  59. Memory controller address hashing
  60. ==================================
  61. If the DDR controller supports address hashing, it can be enabled by hwconfig.
  62. Syntax is:
  63. hwconfig=fsl_ddr:addr_hash=true
  64. Memory controller ECC on/off
  65. ============================
  66. If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
  67. ECC can be turned on/off by hwconfig.
  68. Syntax is
  69. hwconfig=fsl_ddr:ecc=off
  70. Memory testing options for mpc85xx
  71. ==================================
  72. 1. Memory test can be done once U-boot prompt comes up using mtest, or
  73. 2. Memory test can be done with Power-On-Self-Test function, activated at
  74. compile time.
  75. In order to enable the POST memory test, CONFIG_POST needs to be
  76. defined in board configuraiton header file. By default, POST memory test
  77. performs a fast test. A slow test can be enabled by changing the flag at
  78. compiling time. To test memory bigger than 2GB, 36BIT support is needed.
  79. Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
  80. window to physical address so that all physical memory can be tested.
  81. Combination of hwconfig
  82. =======================
  83. Hwconfig can be combined with multiple parameters, for example, on a supported
  84. platform
  85. hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
  86. Table for dynamic ODT for DDR3
  87. ==============================
  88. For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
  89. be needed, depending on the configuration. The numbers in the following tables are
  90. in Ohms.
  91. * denotes dynamic ODT
  92. Two slots system
  93. +-----------------------+----------+---------------+-----------------------------+-----------------------------+
  94. | Configuration | |DRAM controller| Slot 1 | Slot 2 |
  95. +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
  96. | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
  97. + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
  98. | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
  99. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  100. | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
  101. | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  102. | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
  103. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  104. | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
  105. | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  106. | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
  107. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  108. | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
  109. |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  110. | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
  111. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  112. | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
  113. |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  114. | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
  115. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  116. | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
  117. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  118. | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
  119. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  120. |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
  121. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  122. | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
  123. +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  124. Single slot system
  125. +-------------+------------+---------------+-----------------------------+-----------------------------+
  126. | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
  127. |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
  128. | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
  129. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  130. | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
  131. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  132. | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
  133. | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  134. | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
  135. | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  136. | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
  137. +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
  138. | | R1 | off | 75 | 40 | off | off | off |
  139. | Dual Rank |------------+-------+-------+-------+------+-------+------+
  140. | | R2 | off | 75 | 40 | off | off | off |
  141. +-------------+------------+-------+-------+-------+------+-------+------+
  142. | Single Rank | R1 | off | 75 | 40 | off |
  143. +-------------+------------+-------+-------+-------+------+
  144. Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
  145. http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf