sf_vop.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
  4. * Copyright (c) 2015 Google, Inc
  5. * Copyright 2014 Rockchip Inc.
  6. */
  7. #include <common.h>
  8. #include <display.h>
  9. #include <dm.h>
  10. #include <dm/uclass.h>
  11. #include <dm/device.h>
  12. #include <dm/uclass-internal.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <regmap.h>
  16. #include <syscon.h>
  17. #include <video.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <linux/delay.h>
  21. #include <power-domain-uclass.h>
  22. #include <power-domain.h>
  23. #include <clk.h>
  24. #include <video_bridge.h>
  25. #include <power/pmic.h>
  26. #include <panel.h>
  27. #include "sf_vop.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static void iotrace_writel(ulong value, void *ptr)
  30. {
  31. //printf("writel( 0x%08x, %p ) -- 0x%08x\n", value, ptr, readl(ptr));
  32. //readl(ptr);
  33. mdelay(10);
  34. writel(value, ptr);
  35. }
  36. static int sf_vop_power_off(struct udevice *dev)
  37. {
  38. struct udevice *dev_power;
  39. struct power_domain_ops *ops;
  40. struct power_domain power_domain;
  41. int ret;
  42. if (!(gd->flags & GD_FLG_RELOC))
  43. return 0;
  44. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  45. if (ret)
  46. return ret;
  47. ret = device_probe(dev_power);
  48. if (ret) {
  49. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  50. __func__, dev_power->name, ret);
  51. return ret;
  52. }
  53. ops = (struct power_domain_ops *)dev_power->driver->ops;
  54. power_domain.dev = dev_power;
  55. power_domain.id = 4;
  56. ret = ops->off(&power_domain);
  57. if (ret) {
  58. pr_err("ops->0ff() failed: %d\n", ret);
  59. return ret;
  60. }
  61. return 0;
  62. }
  63. static int sf_vop_power(struct udevice *dev)
  64. {
  65. struct udevice *dev_power;
  66. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  67. struct udevice *dev_pmic;
  68. #endif
  69. struct power_domain_ops *ops;
  70. struct power_domain power_domain;
  71. int ret;
  72. if (!(gd->flags & GD_FLG_RELOC))
  73. return 0;
  74. ret = uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev_power);
  75. if (ret)
  76. return ret;
  77. ret = device_probe(dev_power);
  78. if (ret) {
  79. pr_err("%s: device '%s' display won't probe (ret=%d)\n",
  80. __func__, dev_power->name, ret);
  81. return ret;
  82. }
  83. ops = (struct power_domain_ops *)dev_power->driver->ops;
  84. power_domain.dev = dev_power;
  85. power_domain.id = 4;
  86. ret = ops->request(&power_domain);
  87. if (ret) {
  88. pr_err("ops->request() failed: %d\n", ret);
  89. return ret;
  90. }
  91. ret = ops->on(&power_domain);
  92. if (ret) {
  93. pr_err("ops->on() failed: %d\n", ret);
  94. return ret;
  95. }
  96. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_EVB)
  97. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  98. DM_DRIVER_GET(pmic_starfive), &dev_pmic);
  99. if (ret) {
  100. pr_err("failed to find PMIC: %d\n", ret);
  101. return ret;
  102. }
  103. ret = pmic_clrsetbits(dev_pmic, POWER_SW_0_REG, 0x3f, 0x3f);
  104. if (ret) {
  105. pr_err("failed to update SD control register: %d", ret);
  106. return ret;
  107. }
  108. #endif
  109. return 0;
  110. }
  111. static int vout_get_rst_clock_resources(struct udevice *dev)
  112. {
  113. struct sf_vop_priv *priv = dev_get_priv(dev);
  114. int ret;
  115. ret = clk_get_by_name(dev, "disp_axi", &priv->disp_axi);
  116. if (ret) {
  117. pr_err("clk_get_by_name(noc_disp) failed: %d", ret);
  118. return ret;
  119. }
  120. ret = clk_get_by_name(dev, "vout_src", &priv->vout_src);
  121. if (ret) {
  122. pr_err("clk_get_by_name(vout_src) failed: %d\n", ret);
  123. return ret;
  124. }
  125. ret = clk_get_by_name(dev, "top_vout_axi", &priv->top_vout_axi);
  126. if (ret) {
  127. pr_err("clk_get_by_name(top_vout_axi) failed: %d\n", ret);
  128. return ret;
  129. }
  130. ret = clk_get_by_name(dev, "top_vout_ahb", &priv->top_vout_ahb);
  131. if (ret) {
  132. pr_err("clk_get_by_name(top_vout_ahb) failed: %d\n", ret);
  133. return ret;
  134. }
  135. ret = clk_get_by_name(dev, "dc_pix0", &priv->dc_pix0);
  136. if (ret) {
  137. pr_err("clk_get_by_name(dc_pix0) failed: %d\n", ret);
  138. return ret;
  139. }
  140. ret = clk_get_by_name(dev, "dc_pix1", &priv->dc_pix1);
  141. if (ret) {
  142. pr_err("clk_get_by_name(dc_pix1) failed: %d\n", ret);
  143. return ret;
  144. }
  145. ret = clk_get_by_name(dev, "dc_axi", &priv->dc_axi);
  146. if (ret) {
  147. pr_err("clk_get_by_name(dc_axi) failed: %d\n", ret);
  148. return ret;
  149. }
  150. ret = clk_get_by_name(dev, "dc_core", &priv->dc_core);
  151. if (ret) {
  152. pr_err("clk_get_by_name(dc_core) failed: %d\n", ret);
  153. return ret;
  154. }
  155. ret = clk_get_by_name(dev, "dc_ahb", &priv->dc_ahb);
  156. if (ret) {
  157. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  158. return ret;
  159. }
  160. ret = clk_get_by_name(dev, "top_vout_lcd", &priv->top_vout_lcd);
  161. if (ret) {
  162. pr_err("clk_get_by_name(top_vout_lcd) failed: %d\n", ret);
  163. return ret;
  164. }
  165. ret = clk_get_by_name(dev, "hdmitx0_pixelclk", &priv->hdmitx0_pixelclk);
  166. if (ret) {
  167. pr_err("clk_get_by_name(hdmitx0_pixelclk) failed: %d\n", ret);
  168. return ret;
  169. }
  170. ret = clk_get_by_name(dev, "dc8200_pix0", &priv->dc_pix_src);
  171. if (ret) {
  172. pr_err("clk_get_by_name(dc_pix_src) failed: %d\n", ret);
  173. return ret;
  174. }
  175. ret = clk_get_by_name(dev, "dc8200_pix0_out", &priv->dc_pix0_out);
  176. if (ret) {
  177. pr_err("clk_get_by_name(dc_pix0_out) failed: %d\n", ret);
  178. return ret;
  179. }
  180. ret = clk_get_by_name(dev, "dc8200_pix1_out", &priv->dc_pix1_out);
  181. if (ret) {
  182. pr_err("clk_get_by_name(dc_ahb) failed: %d\n", ret);
  183. return ret;
  184. }
  185. ret = reset_get_by_name(dev, "rst_vout_src", &priv->rst_vout_src);
  186. if (ret) {
  187. pr_err("failed to get rst_vout_src reset (ret=%d)\n", ret);
  188. return ret;
  189. }
  190. ret = reset_get_by_name(dev, "rst_axi", &priv->dc8200_rst_axi);
  191. if (ret) {
  192. pr_err("failed to get dc8200_rst_axi reset (ret=%d)\n", ret);
  193. return ret;
  194. }
  195. ret = reset_get_by_name(dev, "rst_ahb", &priv->dc8200_rst_ahb);
  196. if (ret) {
  197. pr_err("failed to get ahb reset (ret=%d)\n", ret);
  198. return ret;
  199. }
  200. ret = reset_get_by_name(dev, "rst_core", &priv->dc8200_rst_core);
  201. if (ret) {
  202. pr_err("failed to get dc8200_rst_core reset (ret=%d)\n", ret);
  203. return ret;
  204. }
  205. ret = reset_get_by_name(dev, "rst_noc_disp", &priv->noc_disp);
  206. if (ret) {
  207. pr_err("failed to get noc_disp reset (ret=%d)\n", ret);
  208. return ret;
  209. }
  210. debug("%s: OK\n", __func__);
  211. return 0;
  212. }
  213. int dc_hw_init(struct udevice *dev)
  214. {
  215. struct sf_vop_priv *priv = dev_get_priv(dev);
  216. u32 revision = readl(priv->regs_hi+DC_HW_REVISION);
  217. u32 cid = readl(priv->regs_hi+DC_HW_CHIP_CID);
  218. debug("%s: revision = %08x\n", __func__,revision);
  219. debug("%s: cid = %08x\n", __func__,cid);
  220. return 0;
  221. }
  222. static int vout_probe_resources_jh7110(struct udevice *dev)
  223. {
  224. struct sf_vop_priv *priv = dev_get_priv(dev);
  225. int ret;
  226. ret = vout_get_rst_clock_resources(dev);
  227. ret = clk_enable(&priv->disp_axi);
  228. if (ret < 0) {
  229. pr_err("clk_enable(noc_disp) failed: %d\n", ret);
  230. return ret;
  231. }
  232. ret = reset_deassert(&priv->noc_disp);
  233. if (ret) {
  234. pr_err("failed to deassert noc_disp reset (ret=%d)\n", ret);
  235. goto free_clock_vout_src;
  236. }
  237. ret = clk_enable(&priv->vout_src);
  238. if (ret < 0) {
  239. pr_err("clk_enable(vout_src) failed: %d\n", ret);
  240. goto free_clock_vout_src;
  241. }
  242. ret = clk_enable(&priv->top_vout_axi);
  243. if (ret < 0) {
  244. pr_err("clk_enable(top_vout_axi) failed: %d\n", ret);
  245. goto free_clock_top_vout_axi;
  246. }
  247. ret = clk_enable(&priv->top_vout_ahb);
  248. if (ret < 0) {
  249. pr_err("clk_enable(top_vout_ahb) failed: %d\n", ret);
  250. goto free_clock_top_vout_ahb;
  251. }
  252. ret = reset_deassert(&priv->rst_vout_src);
  253. if (ret) {
  254. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  255. goto free_clock_dc_pix0;
  256. }
  257. ret = clk_enable(&priv->dc_pix0);
  258. if (ret < 0) {
  259. pr_err("clk_enable(dc_pix0) failed: %d\n", ret);
  260. goto free_clock_dc_pix0;
  261. }
  262. ret = clk_enable(&priv->dc_pix1);
  263. if (ret < 0) {
  264. pr_err("clk_enable(dc_pix1) failed: %d\n", ret);
  265. goto free_clock_dc_pix1;
  266. }
  267. ret = clk_enable(&priv->dc_axi);
  268. if (ret < 0) {
  269. pr_err("clk_enable(dc_axi) failed: %d\n", ret);
  270. goto free_clock_dc_axi;
  271. }
  272. ret = clk_enable(&priv->dc_core);
  273. if (ret < 0) {
  274. pr_err("clk_enable(dc_core) failed: %d\n", ret);
  275. goto free_clock_dc_core;
  276. }
  277. ret = clk_enable(&priv->dc_ahb);
  278. if (ret < 0) {
  279. pr_err("clk_enable(dc_ahb) failed: %d\n", ret);
  280. goto free_clock_dc_ahb;
  281. }
  282. ret = clk_enable(&priv->hdmitx0_pixelclk);
  283. if (ret < 0) {
  284. pr_err("clk_enable(hdmitx0_pixelclk) failed: %d\n", ret);
  285. goto free_clock_hdmitx0_pixelclk;
  286. }
  287. ret = reset_deassert(&priv->dc8200_rst_axi);
  288. if (ret) {
  289. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  290. goto free_reset_dc8200;
  291. }
  292. ret = reset_deassert(&priv->dc8200_rst_core);
  293. if (ret) {
  294. pr_err("failed to deassert dc8200_rst_axi reset (ret=%d)\n", ret);
  295. goto free_reset_dc8200;
  296. }
  297. ret = reset_deassert(&priv->dc8200_rst_ahb);
  298. if (ret) {
  299. pr_err("failed to deassert dc8200_rst_ahb reset (ret=%d)\n", ret);
  300. goto free_reset_dc8200;
  301. }
  302. debug("%s: OK\n", __func__);
  303. return 0;
  304. free_reset_dc8200:
  305. clk_disable(&priv->hdmitx0_pixelclk);
  306. free_clock_hdmitx0_pixelclk:
  307. clk_disable(&priv->dc_ahb);
  308. free_clock_dc_ahb:
  309. clk_disable(&priv->dc_core);
  310. free_clock_dc_core:
  311. clk_disable(&priv->dc_axi);
  312. free_clock_dc_axi:
  313. clk_disable(&priv->dc_pix1);
  314. free_clock_dc_pix1:
  315. clk_disable(&priv->dc_pix0);
  316. free_clock_dc_pix0:
  317. clk_disable(&priv->top_vout_ahb);
  318. free_clock_top_vout_ahb:
  319. clk_disable(&priv->top_vout_axi);
  320. free_clock_top_vout_axi:
  321. clk_disable(&priv->vout_src);
  322. free_clock_vout_src:
  323. clk_disable(&priv->disp_axi);
  324. return ret;
  325. }
  326. static int sf_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
  327. {
  328. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  329. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  330. struct sf_vop_priv *priv = dev_get_priv(dev);
  331. int vop_id, remote_vop_id;
  332. struct display_timing timing;
  333. struct udevice *disp;
  334. int ret;
  335. u32 remote_phandle;
  336. ofnode remote;
  337. const char *compat;
  338. struct display_plat *disp_uc_plat;
  339. debug("%s(%s, 0x%lx, %s)\n", __func__,
  340. dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
  341. struct udevice *panel = NULL;
  342. ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
  343. if (ret)
  344. return ret;
  345. remote = ofnode_get_by_phandle(remote_phandle);
  346. if (!ofnode_valid(remote))
  347. return -EINVAL;
  348. remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
  349. uc_priv->bpix = VIDEO_BPP32;
  350. debug("remote_vop_id %d\n", remote_vop_id);
  351. /*
  352. * The remote-endpoint references into a subnode of the encoder
  353. * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
  354. * the following (assume 'hdmi_in_vopl' to be referenced):
  355. *
  356. * hdmi: hdmi@ff940000 {
  357. * ports {
  358. * hdmi_in: port {
  359. * hdmi_in_vopb: endpoint@0 { ... };
  360. * hdmi_in_vopl: endpoint@1 { ... };
  361. * }
  362. * }
  363. * }
  364. *
  365. * The original code had 3 steps of "walking the parent", but
  366. * a much better (as in: less likely to break if the DTS
  367. * changes) way of doing this is to "find the enclosing device
  368. * of UCLASS_DISPLAY".
  369. */
  370. while (ofnode_valid(remote)) {
  371. remote = ofnode_get_parent(remote);
  372. if (!ofnode_valid(remote)) {
  373. debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
  374. __func__, dev_read_name(dev));
  375. return -EINVAL;
  376. }
  377. debug("%s(%s, 0x%lx,remote %s)\n", __func__,
  378. dev_read_name(dev), fbbase, ofnode_get_name(remote));
  379. uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
  380. if (disp)
  381. break;
  382. uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &disp);
  383. if (disp)
  384. break;
  385. };
  386. compat = ofnode_get_property(remote, "compatible", NULL);
  387. if (!compat) {
  388. debug("%s(%s): Failed to find compatible property\n",
  389. __func__, dev_read_name(dev));
  390. return -EINVAL;
  391. }
  392. if (strstr(compat, "edp")) {
  393. vop_id = VOP_MODE_EDP;
  394. } else if (strstr(compat, "mipi")) {
  395. vop_id = VOP_MODE_MIPI;
  396. } else if (strstr(compat, "hdmi")) {
  397. vop_id = VOP_MODE_HDMI;
  398. } else if (strstr(compat, "cdn-dp")) {
  399. vop_id = VOP_MODE_DP;
  400. } else if (strstr(compat, "lvds")) {
  401. vop_id = VOP_MODE_LVDS;
  402. } else {
  403. debug("%s(%s): Failed to find vop mode for %s\n",
  404. __func__, dev_read_name(dev), compat);
  405. return -EINVAL;
  406. }
  407. debug("vop_id %d,compat = %s\n", vop_id,compat);
  408. if(vop_id == VOP_MODE_HDMI)
  409. {
  410. disp_uc_plat = dev_get_uclass_plat(disp);
  411. debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
  412. disp_uc_plat->source_id = remote_vop_id;
  413. disp_uc_plat->src_dev = dev;
  414. ret = device_probe(disp);
  415. if (ret) {
  416. debug("%s: device '%s' display won't probe (ret=%d)\n",
  417. __func__, dev->name, ret);
  418. return ret;
  419. }
  420. ret = display_enable(disp, 1 << VIDEO_BPP32, &timing);
  421. if (ret) {
  422. debug("%s: Failed to read timings\n", __func__);
  423. return ret;
  424. }
  425. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  426. if (err) {
  427. debug("failed to set %s clock as %s's parent\n",
  428. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  429. return err;
  430. }
  431. ulong new_rate = clk_set_rate(&priv->dc_pix_src, 148500000);
  432. debug("new_rate %ld\n", new_rate);
  433. dc_hw_init(dev);
  434. uc_priv->xsize = 1920;
  435. uc_priv->ysize = 1080;
  436. writel(0xc0001fff, priv->regs_hi+0x00000014);
  437. writel(0x00002000, priv->regs_hi+0x00001cc0);
  438. //writel(uc_plat->base+0x1fa400, priv->regs_hi+0x00001530);
  439. writel(0x00000000, priv->regs_hi+0x00001800);
  440. writel(0x00000000, priv->regs_hi+0x000024d8);
  441. writel(0x021c0780, priv->regs_hi+0x000024e0);
  442. writel(0x021c0780, priv->regs_hi+0x00001810);
  443. writel(uc_plat->base, priv->regs_hi+0x00001400);
  444. writel(0x00001e00, priv->regs_hi+0x00001408);
  445. writel(0x00000f61, priv->regs_hi+0x00001ce8);
  446. writel(0x00002042, priv->regs_hi+0x00002510);
  447. writel(0x808a3156, priv->regs_hi+0x00002508);
  448. writel(0x8008e1b2, priv->regs_hi+0x00002500);
  449. writel(0x18000000, priv->regs_hi+0x00001518);
  450. writel(0x00003000, priv->regs_hi+0x00001cc0);
  451. writel(0x00060000, priv->regs_hi+0x00001540);
  452. writel(0x00000001, priv->regs_hi+0x00002540);
  453. writel(0x80060000, priv->regs_hi+0x00001540);
  454. writel(0x00060000, priv->regs_hi+0x00001544);
  455. writel(0x00000002, priv->regs_hi+0x00002544);
  456. writel(0x80060000, priv->regs_hi+0x00001544);
  457. writel(0x00060000, priv->regs_hi+0x00001548);
  458. writel(0x0000000c, priv->regs_hi+0x00002548);
  459. writel(0x80060000, priv->regs_hi+0x00001548);
  460. writel(0x00060000, priv->regs_hi+0x0000154c);
  461. writel(0x0000000d, priv->regs_hi+0x0000254c);
  462. writel(0x80060000, priv->regs_hi+0x0000154c);
  463. writel(0x00000001, priv->regs_hi+0x00002518);
  464. writel(0x00000000, priv->regs_hi+0x00001a28);
  465. writel(0x08980780, priv->regs_hi+0x00001430);
  466. writel(0x440207d8, priv->regs_hi+0x00001438);
  467. writel(0x04650438, priv->regs_hi+0x00001440);
  468. writel(0x4220843c, priv->regs_hi+0x00001448);
  469. writel(0x00000000, priv->regs_hi+0x000014b0);
  470. writel(0x000000d2, priv->regs_hi+0x00001cd0);
  471. writel(0x00000005, priv->regs_hi+0x000014b8);
  472. writel(0x00000052, priv->regs_hi+0x000014d0);
  473. writel(0xdeadbeef, priv->regs_hi+0x00001528);
  474. writel(0x00001111, priv->regs_hi+0x00001418);
  475. writel(0x00000000, priv->regs_hi+0x00001410);
  476. writel(0x00000000, priv->regs_hi+0x00002518);
  477. writel(0x00200024, priv->regs_hi+0x00001468);
  478. writel(0x00000000, priv->regs_hi+0x00001484);
  479. writel(0x00200024, priv->regs_hi+0x00001468);
  480. writel(0x00000c24, priv->regs_hi+0x000024e8);
  481. writel(0x00000000, priv->regs_hi+0x000024fc);
  482. writel(0x00000c24, priv->regs_hi+0x000024e8);
  483. writel(0x00000001, priv->regs_hi+0x00001ccc);
  484. priv->hdmi_logo = true;
  485. return 0;
  486. }
  487. if(vop_id == VOP_MODE_MIPI)
  488. {
  489. ret = device_probe(disp);
  490. if (ret) {
  491. debug("%s: device '%s' display won't probe (ret=%d)\n",
  492. __func__, dev->name, ret);
  493. return ret;
  494. }
  495. ret = video_bridge_attach(disp);
  496. if (ret) {
  497. debug("fail to attach bridge\n");
  498. return ret;
  499. }
  500. ret = video_bridge_set_backlight(disp, 80);
  501. if (ret) {
  502. debug("dp: failed to set backlight\n");
  503. return ret;
  504. }
  505. ret = uclass_first_device_err(UCLASS_PANEL, &panel);
  506. if (ret) {
  507. if (ret != -ENODEV)
  508. debug("panel device error %d\n", ret);
  509. return ret;
  510. }
  511. ret = panel_get_display_timing(panel, &timing);
  512. if (ret) {
  513. ret = ofnode_decode_display_timing(dev_ofnode(panel),
  514. 0, &timing);
  515. if (ret) {
  516. debug("decode display timing error %d\n", ret);
  517. return ret;
  518. }
  519. }
  520. int err = clk_set_parent(&priv->dc_pix0, &priv->dc_pix_src);
  521. if (err) {
  522. debug("failed to set %s clock as %s's parent\n",
  523. priv->dc_pix_src.dev->name, priv->dc_pix0.dev->name);
  524. return err;
  525. }
  526. ulong new_rate = clk_set_rate(&priv->dc_pix_src, timing.pixelclock.typ);
  527. debug("new_rate %ld\n", new_rate);
  528. dc_hw_init(dev);
  529. uc_priv->xsize = timing.hactive.typ;
  530. uc_priv->ysize = timing.vactive.typ;
  531. if (IS_ENABLED(CONFIG_VIDEO_COPY))
  532. uc_plat->copy_base = uc_plat->base - uc_plat->size / 2;
  533. writel(0xc0001fff, priv->regs_hi+0x00000014); //csr_reg
  534. writel(0x000000e8, priv->regs_hi+0x00001a38); //csr_reg
  535. writel(0x00002000, priv->regs_hi+0x00001cc0); //csr_reg
  536. writel(0x00000000, priv->regs_hi+0x000024d8); //csr_reg
  537. writel(0x03c00438, priv->regs_hi+0x000024e0); //csr_reg
  538. writel(0x03c00438, priv->regs_hi+0x00001810); //csr_reg
  539. writel(uc_plat->base, priv->regs_hi+0x00001400);
  540. writel(0x000010e0, priv->regs_hi+0x00001408); //csr_reg
  541. writel(0x000fb00b, priv->regs_hi+0x00001ce8); //csr_reg
  542. writel(0x0000a9a3, priv->regs_hi+0x00002510); //csr_reg
  543. writel(0x2c4e6f06, priv->regs_hi+0x00002508); //csr_reg
  544. writel(0xe6daec4f, priv->regs_hi+0x00002500); //csr_reg
  545. writel(0x18220000, priv->regs_hi+0x00001518); //csr_reg
  546. writel(0x00003000, priv->regs_hi+0x00001cc0); //csr_reg
  547. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  548. writel(0x00030000, priv->regs_hi+0x00001cc4); //csr_reg
  549. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  550. writel(0x00000001, priv->regs_hi+0x00002540); //csr_reg
  551. writel(0x00050c1a, priv->regs_hi+0x00001540); //csr_reg
  552. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  553. writel(0x00000002, priv->regs_hi+0x00002544); //csr_reg
  554. writel(0x4016120c, priv->regs_hi+0x00001544); //csr_reg
  555. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  556. writel(0x00000004, priv->regs_hi+0x00002548); //csr_reg
  557. writel(0x001b1208, priv->regs_hi+0x00001548); //csr_reg
  558. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  559. writel(0x00000005, priv->regs_hi+0x0000254c); //csr_reg
  560. writel(0x0016110e, priv->regs_hi+0x0000154c); //csr_reg
  561. writel(0x00000001, priv->regs_hi+0x00002518); //csr_reg
  562. writel(0x00000000, priv->regs_hi+0x00001a28); //csr_reg
  563. writel(0x03840320, priv->regs_hi+0x00001430); //csr_reg, hsize, htotal
  564. writel(0xc1bf837a, priv->regs_hi+0x00001438); //csr_reg, hsize blanking
  565. writel(0x022601e0, priv->regs_hi+0x00001440); //csr_reg, vsize
  566. writel(0xc110021c, priv->regs_hi+0x00001448); //csr_reg, vsize blanking
  567. writel(0x00000000, priv->regs_hi+0x000014b0); //csr_reg
  568. writel(0x000000e2, priv->regs_hi+0x00001cd0); //csr_reg
  569. writel(0x000000af, priv->regs_hi+0x000014d0); //csr_reg
  570. writel(0x00000005, priv->regs_hi+0x000014b8); //csr_reg
  571. writel(0x8dd0b774, priv->regs_hi+0x00001528); //csr_reg
  572. writel(0x00001111, priv->regs_hi+0x00001418); //csr_reg
  573. writel(0x00000000, priv->regs_hi+0x00001410); //csr_reg
  574. writel(0x00000000, priv->regs_hi+0x00002518); //csr_reg
  575. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  576. writel(0x00000000, priv->regs_hi+0x00001484); //csr_reg
  577. writel(0x00000006, priv->regs_hi+0x00001468); //csr_reg
  578. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  579. writel(0x00000000, priv->regs_hi+0x000024fc); //csr_reg
  580. writel(0x00011b25, priv->regs_hi+0x000024e8); //csr_reg
  581. writel(0x00000001, priv->regs_hi+0x00001ccc); //csr_reg
  582. priv->mipi_logo = true;
  583. return 0;
  584. }
  585. return 0;
  586. }
  587. static int sf_vop_probe(struct udevice *dev)
  588. {
  589. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  590. struct sf_vop_priv *priv = dev_get_priv(dev);
  591. ofnode port, node;
  592. int ret;
  593. sf_vop_power(dev);
  594. mdelay(50);
  595. priv->regs_hi = dev_remap_addr_name(dev, "hi");
  596. if (!priv->regs_hi)
  597. return -EINVAL;
  598. priv->regs_low = dev_remap_addr_name(dev, "low");
  599. if (!priv->regs_low)
  600. return -EINVAL;
  601. priv->hdmi_logo = false;
  602. priv->mipi_logo = false;
  603. vout_probe_resources_jh7110(dev);
  604. port = dev_read_subnode(dev, "port");
  605. if (!ofnode_valid(port)) {
  606. debug("%s(%s): 'port' subnode not found\n",
  607. __func__, dev_read_name(dev));
  608. return -EINVAL;
  609. }
  610. for (node = ofnode_first_subnode(port);
  611. ofnode_valid(node);
  612. node = dev_read_next_subnode(node)) {
  613. ret = sf_display_init(dev, plat->base, node);
  614. if (ret)
  615. debug("Device failed: ret=%d\n", ret);
  616. if (!ret)
  617. break;
  618. }
  619. video_set_flush_dcache(dev, 1);
  620. return 0;
  621. }
  622. static int sf_vop_remove(struct udevice *dev)
  623. {
  624. struct sf_vop_priv *priv = dev_get_priv(dev);
  625. debug("sf_vop_remove-------\n");
  626. int ret;
  627. if(priv->mipi_logo == true)
  628. return 0;
  629. iotrace_writel( 0x00000000, priv->regs_hi+0x1cc0 );
  630. iotrace_writel( 0x00000000, priv->regs_hi+0x24e0 );
  631. iotrace_writel( 0x00000000, priv->regs_hi+0x1810 );
  632. iotrace_writel( 0x00000000, priv->regs_hi+0x1400 );
  633. iotrace_writel( 0x00000000, priv->regs_hi+0x1408 );
  634. iotrace_writel( 0x00000000, priv->regs_hi+0x1ce8 );
  635. iotrace_writel( 0x00000000, priv->regs_hi+0x2510 );
  636. iotrace_writel( 0x00000000, priv->regs_hi+0x2508 );
  637. iotrace_writel( 0x00000000, priv->regs_hi+0x2500 );
  638. iotrace_writel( 0x00000000, priv->regs_hi+0x1518 );
  639. iotrace_writel( 0x00000000, priv->regs_hi+0x1540 );
  640. iotrace_writel( 0x00000000, priv->regs_hi+0x2540 );
  641. iotrace_writel( 0x00000000, priv->regs_hi+0x1544 );
  642. iotrace_writel( 0x00000000, priv->regs_hi+0x2544 );
  643. iotrace_writel( 0x00000000, priv->regs_hi+0x1548 );
  644. iotrace_writel( 0x00000000, priv->regs_hi+0x2548 );
  645. iotrace_writel( 0x00000000, priv->regs_hi+0x154c );
  646. iotrace_writel( 0x00000000, priv->regs_hi+0x254c );
  647. iotrace_writel( 0x00000000, priv->regs_hi+0x2518 );
  648. iotrace_writel( 0x00000e07, priv->regs_hi+0x1a28 );
  649. iotrace_writel( 0x00000000, priv->regs_hi+0x1430 );
  650. iotrace_writel( 0x00000000, priv->regs_hi+0x1438 );
  651. iotrace_writel( 0x00000000, priv->regs_hi+0x1440 );
  652. iotrace_writel( 0x00000000, priv->regs_hi+0x1448 );
  653. iotrace_writel( 0x00000000, priv->regs_hi+0x14b0 );
  654. iotrace_writel( 0x00000000, priv->regs_hi+0x1cd0 );
  655. iotrace_writel( 0x00000000, priv->regs_hi+0x14b8 );
  656. iotrace_writel( 0x00000000, priv->regs_hi+0x14d0 );
  657. iotrace_writel( 0x00000000, priv->regs_hi+0x1528 );
  658. iotrace_writel( 0x00000100, priv->regs_hi+0x1418 );
  659. iotrace_writel( 0x00000000, priv->regs_hi+0x1410 );
  660. iotrace_writel( 0x00000001, priv->regs_hi+0x2518 );
  661. iotrace_writel( 0x00000000, priv->regs_hi+0x1468 );
  662. iotrace_writel( 0x00000001, priv->regs_hi+0x1484 );
  663. iotrace_writel( 0x00000000, priv->regs_hi+0x24e8 );
  664. iotrace_writel( 0x00000001, priv->regs_hi+0x24fc );
  665. iotrace_writel( 0x00000000, priv->regs_hi+0x1ccc );
  666. ret = reset_assert(&priv->dc8200_rst_axi);
  667. if (ret) {
  668. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  669. return ret;
  670. }
  671. ret = reset_assert(&priv->dc8200_rst_core);
  672. if (ret) {
  673. pr_err("failed to assert dc8200_rst_axi reset (ret=%d)\n", ret);
  674. return ret;
  675. }
  676. ret = reset_assert(&priv->dc8200_rst_ahb);
  677. if (ret) {
  678. pr_err("failed to assert dc8200_rst_ahb reset (ret=%d)\n", ret);
  679. return ret;
  680. }
  681. clk_set_rate(&priv->dc_pix_src, 74250000);
  682. clk_disable(&priv->hdmitx0_pixelclk);
  683. clk_disable(&priv->dc_ahb);
  684. clk_disable(&priv->dc_core);
  685. clk_disable(&priv->dc_axi);
  686. clk_disable(&priv->dc_pix1);
  687. clk_disable(&priv->dc_pix0);
  688. ret = reset_assert(&priv->rst_vout_src);
  689. if (ret) {
  690. pr_err("failed to deassert rst_vout_src reset (ret=%d)\n", ret);
  691. return ret;
  692. }
  693. clk_disable(&priv->top_vout_ahb);
  694. clk_disable(&priv->top_vout_axi);
  695. clk_disable(&priv->vout_src);
  696. clk_disable(&priv->disp_axi);
  697. reset_assert(&priv->noc_disp);
  698. sf_vop_power_off(dev);
  699. return 0;
  700. }
  701. struct rkvop_driverdata rk3288_driverdata = {
  702. .features = VOP_FEATURE_OUTPUT_10BIT,
  703. };
  704. static const struct udevice_id sf_dc_ids[] = {
  705. { .compatible = "starfive,sf-dc8200",
  706. .data = (ulong)&rk3288_driverdata },
  707. { }
  708. };
  709. static const struct video_ops sf_vop_ops = {
  710. };
  711. int sf_vop_bind(struct udevice *dev)
  712. {
  713. struct video_uc_plat *plat = dev_get_uclass_plat(dev);
  714. plat->size = 4 * (CONFIG_VIDEO_STARFIVE_MAX_XRES *
  715. CONFIG_VIDEO_STARFIVE_MAX_YRES);
  716. debug("%s,%d,plat->size = %d\n",__func__,__LINE__,plat->size);
  717. return 0;
  718. }
  719. U_BOOT_DRIVER(starfive_dc8200) = {
  720. .name = "starfive_dc8200",
  721. .id = UCLASS_VIDEO,
  722. .of_match = sf_dc_ids,
  723. .ops = &sf_vop_ops,
  724. .bind = sf_vop_bind,
  725. .probe = sf_vop_probe,
  726. .remove = sf_vop_remove,
  727. .priv_auto = sizeof(struct sf_vop_priv),
  728. .flags = DM_FLAG_OS_PREPARE,
  729. };