io.h 13 KB

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  1. /*
  2. * Copyright (C) 2017 Andes Technology Corporation
  3. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0
  6. *
  7. */
  8. #ifndef __ASM_RISCV_IO_H
  9. #define __ASM_RISCV_IO_H
  10. #ifdef __KERNEL__
  11. #include <linux/types.h>
  12. #include <asm/byteorder.h>
  13. static inline void sync(void)
  14. {
  15. }
  16. /*
  17. * Given a physical address and a length, return a virtual address
  18. * that can be used to access the memory range with the caching
  19. * properties specified by "flags".
  20. */
  21. #define MAP_NOCACHE (0)
  22. #define MAP_WRCOMBINE (0)
  23. #define MAP_WRBACK (0)
  24. #define MAP_WRTHROUGH (0)
  25. #ifdef CONFIG_ARCH_MAP_SYSMEM
  26. static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
  27. {
  28. if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
  29. paddr = paddr | 0x40000000;
  30. return (void *)(uintptr_t)paddr;
  31. }
  32. static inline void *unmap_sysmem(const void *vaddr)
  33. {
  34. phys_addr_t paddr = (phys_addr_t)vaddr;
  35. paddr = paddr & ~0x40000000;
  36. return (void *)(uintptr_t)paddr;
  37. }
  38. static inline phys_addr_t map_to_sysmem(const void *ptr)
  39. {
  40. return (phys_addr_t)(uintptr_t)ptr;
  41. }
  42. #endif
  43. static inline void *
  44. map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
  45. {
  46. return (void *)paddr;
  47. }
  48. /*
  49. * Take down a mapping set up by map_physmem().
  50. */
  51. static inline void unmap_physmem(void *vaddr, unsigned long flags)
  52. {
  53. }
  54. static inline phys_addr_t virt_to_phys(void *vaddr)
  55. {
  56. return (phys_addr_t)(vaddr);
  57. }
  58. /*
  59. * Generic virtual read/write. Note that we don't support half-word
  60. * read/writes. We define __arch_*[bl] here, and leave __arch_*w
  61. * to the architecture specific code.
  62. */
  63. #define __arch_getb(a) (*(unsigned char *)(a))
  64. #define __arch_getw(a) (*(unsigned short *)(a))
  65. #define __arch_getl(a) (*(unsigned int *)(a))
  66. #define __arch_getq(a) (*(unsigned long *)(a))
  67. #define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
  68. #define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
  69. #define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
  70. #define __arch_putq(v, a) (*(unsigned long *)(a) = (v))
  71. #define __raw_writeb(v, a) __arch_putb(v, a)
  72. #define __raw_writew(v, a) __arch_putw(v, a)
  73. #define __raw_writel(v, a) __arch_putl(v, a)
  74. #define __raw_writeq(v, a) __arch_putq(v, a)
  75. #define __raw_readb(a) __arch_getb(a)
  76. #define __raw_readw(a) __arch_getw(a)
  77. #define __raw_readl(a) __arch_getl(a)
  78. #define __raw_readq(a) __arch_getq(a)
  79. /*
  80. * TODO: The kernel offers some more advanced versions of barriers, it might
  81. * have some advantages to use them instead of the simple one here.
  82. */
  83. #define dmb() __asm__ __volatile__ ("" : : : "memory")
  84. #define __iormb() dmb()
  85. #define __iowmb() dmb()
  86. static inline void writeb(u8 val, volatile void __iomem *addr)
  87. {
  88. __iowmb();
  89. __arch_putb(val, addr);
  90. }
  91. static inline void writew(u16 val, volatile void __iomem *addr)
  92. {
  93. __iowmb();
  94. __arch_putw(val, addr);
  95. }
  96. static inline void writel(u32 val, volatile void __iomem *addr)
  97. {
  98. __iowmb();
  99. __arch_putl(val, addr);
  100. }
  101. static inline void writeq(u64 val, volatile void __iomem *addr)
  102. {
  103. __iowmb();
  104. __arch_putq(val, addr);
  105. }
  106. static inline u8 readb(const volatile void __iomem *addr)
  107. {
  108. u8 val;
  109. val = __arch_getb(addr);
  110. __iormb();
  111. return val;
  112. }
  113. static inline u16 readw(const volatile void __iomem *addr)
  114. {
  115. u16 val;
  116. val = __arch_getw(addr);
  117. __iormb();
  118. return val;
  119. }
  120. static inline u32 readl(const volatile void __iomem *addr)
  121. {
  122. u32 val;
  123. val = __arch_getl(addr);
  124. __iormb();
  125. return val;
  126. }
  127. static inline u64 readq(const volatile void __iomem *addr)
  128. {
  129. u32 val;
  130. val = __arch_getq(addr);
  131. __iormb();
  132. return val;
  133. }
  134. /*
  135. * The compiler seems to be incapable of optimising constants
  136. * properly. Spell it out to the compiler in some cases.
  137. * These are only valid for small values of "off" (< 1<<12)
  138. */
  139. #define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
  140. #define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
  141. #define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
  142. #define __raw_base_readb(base, off) __arch_base_getb(base, off)
  143. #define __raw_base_readw(base, off) __arch_base_getw(base, off)
  144. #define __raw_base_readl(base, off) __arch_base_getl(base, off)
  145. #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
  146. #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
  147. #define out_le32(a, v) out_arch(l, le32, a, v)
  148. #define out_le16(a, v) out_arch(w, le16, a, v)
  149. #define in_le32(a) in_arch(l, le32, a)
  150. #define in_le16(a) in_arch(w, le16, a)
  151. #define out_be32(a, v) out_arch(l, be32, a, v)
  152. #define out_be16(a, v) out_arch(w, be16, a, v)
  153. #define in_be32(a) in_arch(l, be32, a)
  154. #define in_be16(a) in_arch(w, be16, a)
  155. #define out_8(a, v) __raw_writeb(v, a)
  156. #define in_8(a) __raw_readb(a)
  157. /*
  158. * Clear and set bits in one shot. These macros can be used to clear and
  159. * set multiple bits in a register using a single call. These macros can
  160. * also be used to set a multiple-bit bit pattern using a mask, by
  161. * specifying the mask in the 'clear' parameter and the new bit pattern
  162. * in the 'set' parameter.
  163. */
  164. #define clrbits(type, addr, clear) \
  165. out_##type((addr), in_##type(addr) & ~(clear))
  166. #define setbits(type, addr, set) \
  167. out_##type((addr), in_##type(addr) | (set))
  168. #define clrsetbits(type, addr, clear, set) \
  169. out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
  170. #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
  171. #define setbits_be32(addr, set) setbits(be32, addr, set)
  172. #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
  173. #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
  174. #define setbits_le32(addr, set) setbits(le32, addr, set)
  175. #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
  176. #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
  177. #define setbits_be16(addr, set) setbits(be16, addr, set)
  178. #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
  179. #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
  180. #define setbits_le16(addr, set) setbits(le16, addr, set)
  181. #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
  182. #define clrbits_8(addr, clear) clrbits(8, addr, clear)
  183. #define setbits_8(addr, set) setbits(8, addr, set)
  184. #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
  185. /*
  186. * Now, pick up the machine-defined IO definitions
  187. * #include <asm/arch/io.h>
  188. */
  189. /*
  190. * IO port access primitives
  191. * -------------------------
  192. *
  193. * The NDS32 doesn't have special IO access instructions just like ARM;
  194. * all IO is memory mapped.
  195. * Note that these are defined to perform little endian accesses
  196. * only. Their primary purpose is to access PCI and ISA peripherals.
  197. *
  198. * Note that for a big endian machine, this implies that the following
  199. * big endian mode connectivity is in place, as described by numerious
  200. * ARM documents:
  201. *
  202. * PCI: D0-D7 D8-D15 D16-D23 D24-D31
  203. * ARM: D24-D31 D16-D23 D8-D15 D0-D7
  204. *
  205. * The machine specific io.h include defines __io to translate an "IO"
  206. * address to a memory address.
  207. *
  208. * Note that we prevent GCC re-ordering or caching values in expressions
  209. * by introducing sequence points into the in*() definitions. Note that
  210. * __raw_* do not guarantee this behaviour.
  211. *
  212. * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
  213. */
  214. #ifdef __io
  215. #define outb(v, p) __raw_writeb(v, __io(p))
  216. #define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
  217. #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
  218. #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
  219. #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
  220. #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
  221. #define outsb(p, d, l) writesb(__io(p), d, l)
  222. #define outsw(p, d, l) writesw(__io(p), d, l)
  223. #define outsl(p, d, l) writesl(__io(p), d, l)
  224. #define insb(p, d, l) readsb(__io(p), d, l)
  225. #define insw(p, d, l) readsw(__io(p), d, l)
  226. #define insl(p, d, l) readsl(__io(p), d, l)
  227. static inline void readsb(unsigned int *addr, void *data, int bytelen)
  228. {
  229. unsigned char *ptr;
  230. unsigned char *ptr2;
  231. ptr = (unsigned char *)addr;
  232. ptr2 = (unsigned char *)data;
  233. while (bytelen) {
  234. *ptr2 = *ptr;
  235. ptr2++;
  236. bytelen--;
  237. }
  238. }
  239. static inline void readsw(unsigned int *addr, void *data, int wordlen)
  240. {
  241. unsigned short *ptr;
  242. unsigned short *ptr2;
  243. ptr = (unsigned short *)addr;
  244. ptr2 = (unsigned short *)data;
  245. while (wordlen) {
  246. *ptr2 = *ptr;
  247. ptr2++;
  248. wordlen--;
  249. }
  250. }
  251. static inline void readsl(unsigned int *addr, void *data, int longlen)
  252. {
  253. unsigned int *ptr;
  254. unsigned int *ptr2;
  255. ptr = (unsigned int *)addr;
  256. ptr2 = (unsigned int *)data;
  257. while (longlen) {
  258. *ptr2 = *ptr;
  259. ptr2++;
  260. longlen--;
  261. }
  262. }
  263. static inline void writesb(unsigned int *addr, const void *data, int bytelen)
  264. {
  265. unsigned char *ptr;
  266. unsigned char *ptr2;
  267. ptr = (unsigned char *)addr;
  268. ptr2 = (unsigned char *)data;
  269. while (bytelen) {
  270. *ptr = *ptr2;
  271. ptr2++;
  272. bytelen--;
  273. }
  274. }
  275. static inline void writesw(unsigned int *addr, const void *data, int wordlen)
  276. {
  277. unsigned short *ptr;
  278. unsigned short *ptr2;
  279. ptr = (unsigned short *)addr;
  280. ptr2 = (unsigned short *)data;
  281. while (wordlen) {
  282. *ptr = *ptr2;
  283. ptr2++;
  284. wordlen--;
  285. }
  286. }
  287. static inline void writesl(unsigned int *addr, const void *data, int longlen)
  288. {
  289. unsigned int *ptr;
  290. unsigned int *ptr2;
  291. ptr = (unsigned int *)addr;
  292. ptr2 = (unsigned int *)data;
  293. while (longlen) {
  294. *ptr = *ptr2;
  295. ptr2++;
  296. longlen--;
  297. }
  298. }
  299. #endif
  300. #define outb_p(val, port) outb((val), (port))
  301. #define outw_p(val, port) outw((val), (port))
  302. #define outl_p(val, port) outl((val), (port))
  303. #define inb_p(port) inb((port))
  304. #define inw_p(port) inw((port))
  305. #define inl_p(port) inl((port))
  306. #define outsb_p(port, from, len) outsb(port, from, len)
  307. #define outsw_p(port, from, len) outsw(port, from, len)
  308. #define outsl_p(port, from, len) outsl(port, from, len)
  309. #define insb_p(port, to, len) insb(port, to, len)
  310. #define insw_p(port, to, len) insw(port, to, len)
  311. #define insl_p(port, to, len) insl(port, to, len)
  312. /*
  313. * DMA-consistent mapping functions. These allocate/free a region of
  314. * uncached, unwrite-buffered mapped memory space for use with DMA
  315. * devices. This is the "generic" version. The PCI specific version
  316. * is in pci.h
  317. */
  318. /*
  319. * String version of IO memory access ops:
  320. */
  321. /*
  322. * If this architecture has PCI memory IO, then define the read/write
  323. * macros. These should only be used with the cookie passed from
  324. * ioremap.
  325. */
  326. #ifdef __mem_pci
  327. #define readb(c) ({ unsigned int __v = \
  328. __raw_readb(__mem_pci(c)); __v; })
  329. #define readw(c) ({ unsigned int __v = \
  330. le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
  331. #define readl(c) ({ unsigned int __v = \
  332. le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
  333. #define writeb(v, c) __raw_writeb(v, __mem_pci(c))
  334. #define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
  335. #define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
  336. #define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
  337. #define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
  338. #define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
  339. #define eth_io_copy_and_sum(s, c, l, b) \
  340. eth_copy_and_sum((s), __mem_pci(c), (l), (b))
  341. static inline int
  342. check_signature(unsigned long io_addr, const unsigned char *signature,
  343. int length)
  344. {
  345. int retval = 0;
  346. do {
  347. if (readb(io_addr) != *signature)
  348. goto out;
  349. io_addr++;
  350. signature++;
  351. length--;
  352. } while (length);
  353. retval = 1;
  354. out:
  355. return retval;
  356. }
  357. #endif /* __mem_pci */
  358. /*
  359. * If this architecture has ISA IO, then define the isa_read/isa_write
  360. * macros.
  361. */
  362. #ifdef __mem_isa
  363. #define isa_readb(addr) __raw_readb(__mem_isa(addr))
  364. #define isa_readw(addr) __raw_readw(__mem_isa(addr))
  365. #define isa_readl(addr) __raw_readl(__mem_isa(addr))
  366. #define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
  367. #define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
  368. #define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
  369. #define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
  370. #define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
  371. #define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
  372. #define isa_eth_io_copy_and_sum(a, b, c, d) \
  373. eth_copy_and_sum((a), __mem_isa(b), (c), (d))
  374. static inline int
  375. isa_check_signature(unsigned long io_addr, const unsigned char *signature,
  376. int length)
  377. {
  378. int retval = 0;
  379. do {
  380. if (isa_readb(io_addr) != *signature)
  381. goto out;
  382. io_addr++;
  383. signature++;
  384. length--;
  385. } while (length);
  386. retval = 1;
  387. out:
  388. return retval;
  389. }
  390. #else /* __mem_isa */
  391. #define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
  392. #define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
  393. #define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
  394. #define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
  395. #define isa_writew(val, addr) __readwrite_bug("isa_writew")
  396. #define isa_writel(val, addr) __readwrite_bug("isa_writel")
  397. #define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
  398. #define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
  399. #define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
  400. #define isa_eth_io_copy_and_sum(a, b, c, d) \
  401. __readwrite_bug("isa_eth_io_copy_and_sum")
  402. #define isa_check_signature(io, sig, len) (0)
  403. #endif /* __mem_isa */
  404. #endif /* __KERNEL__ */
  405. #endif /* __ASM_RISCV_IO_H */