cache.h 577 B

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  1. /*
  2. * Copyright (C) 2017 Andes Technology Corporation
  3. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef _ASM_RISCV_CACHE_H
  8. #define _ASM_RISCV_CACHE_H
  9. /*
  10. * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
  11. * We use that value for aligning DMA buffers unless the board config has
  12. * specified an alternate cache line size.
  13. */
  14. #ifdef CONFIG_SYS_CACHELINE_SIZE
  15. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  16. #else
  17. #define ARCH_DMA_MINALIGN 32
  18. #endif
  19. #endif /* _ASM_RISCV_CACHE_H */