developerbox.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * u-boot/board/socionext/developerbox/developerbox.c
  4. *
  5. * Copyright (C) 2016-2017 Socionext Inc.
  6. * Copyright (C) 2021 Linaro Ltd.
  7. */
  8. #include <asm/types.h>
  9. #include <asm/armv8/mmu.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <common.h>
  13. #include <env_internal.h>
  14. #include <fdt_support.h>
  15. #include <log.h>
  16. static struct mm_region sc2a11_mem_map[] = {
  17. {
  18. .virt = 0x0UL,
  19. .phys = 0x0UL,
  20. .size = 0x80000000UL,
  21. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  22. PTE_BLOCK_OUTER_SHARE
  23. }, {
  24. /* 1st DDR block */
  25. .virt = 0x80000000UL,
  26. .phys = 0x80000000UL,
  27. .size = PHYS_SDRAM_SIZE,
  28. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  29. PTE_BLOCK_OUTER_SHARE
  30. }, {
  31. /* 2nd DDR place holder */
  32. 0,
  33. }, {
  34. /* 3rd DDR place holder */
  35. 0,
  36. }, {
  37. /* List terminator */
  38. 0,
  39. }
  40. };
  41. struct mm_region *mem_map = sc2a11_mem_map;
  42. #define DDR_REGION_INDEX(i) (1 + (i))
  43. #define MAX_DDR_REGIONS 3
  44. struct draminfo_entry {
  45. u64 base;
  46. u64 size;
  47. };
  48. struct draminfo {
  49. u32 nr_regions;
  50. u32 reserved;
  51. struct draminfo_entry entry[3];
  52. };
  53. struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
  54. DECLARE_GLOBAL_DATA_PTR;
  55. #define LOAD_OFFSET 0x100
  56. /*
  57. * Miscellaneous platform dependent initialisations
  58. */
  59. int board_init(void)
  60. {
  61. gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
  62. gd->env_addr = (ulong)&default_environment[0];
  63. return 0;
  64. }
  65. int ft_board_setup(void *blob, struct bd_info *bd)
  66. {
  67. /* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
  68. fdt_del_node_and_alias(blob, "spi_nor");
  69. fdt_del_node_and_alias(blob, "i2c0");
  70. return 0;
  71. }
  72. /*
  73. * DRAM configuration
  74. */
  75. int dram_init(void)
  76. {
  77. struct draminfo_entry *ent = synquacer_draminfo->entry;
  78. struct mm_region *mr;
  79. int i, ri;
  80. if (synquacer_draminfo->nr_regions < 1) {
  81. log_err("Failed to get correct DRAM information\n");
  82. return -1;
  83. }
  84. /*
  85. * U-Boot RAM size must be under the first DRAM region so that it doesn't
  86. * access secure memory which is at the end of the first DRAM region.
  87. */
  88. gd->ram_size = ent[0].size;
  89. /* Update memory region maps */
  90. for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
  91. if (i >= MAX_DDR_REGIONS)
  92. break;
  93. ri = DDR_REGION_INDEX(i);
  94. mem_map[ri].phys = ent[i].base;
  95. mem_map[ri].size = ent[i].size;
  96. if (i == 0)
  97. continue;
  98. mr = &mem_map[DDR_REGION_INDEX(0)];
  99. mem_map[ri].virt = mr->virt + mr->size;
  100. mem_map[ri].attrs = mr->attrs;
  101. }
  102. return 0;
  103. }
  104. int dram_init_banksize(void)
  105. {
  106. struct draminfo_entry *ent = synquacer_draminfo->entry;
  107. int i;
  108. for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
  109. if (i < synquacer_draminfo->nr_regions) {
  110. debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
  111. gd->bd->bi_dram[i].start = ent[i].base;
  112. gd->bd->bi_dram[i].size = ent[i].size;
  113. }
  114. }
  115. return 0;
  116. }
  117. int print_cpuinfo(void)
  118. {
  119. printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
  120. return 0;
  121. }