CPCI4052.h 13 KB

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  1. /*
  2. * (C) Copyright 2001-2004
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. /*
  8. * board/config.h - configuration options, board specific
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. * (easy to change)
  15. */
  16. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  17. #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
  18. #define CONFIG_CPCI405_VER2 1 /* ...version 2 */
  19. #undef CONFIG_CPCI405_6U /* enable this for 6U boards */
  20. #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  21. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  22. #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
  23. #undef CONFIG_BOOTARGS
  24. #undef CONFIG_BOOTCOMMAND
  25. #define CONFIG_PREBOOT /* enable preboot variable */
  26. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  27. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  28. #define CONFIG_PPC4xx_EMAC
  29. #define CONFIG_MII 1 /* MII PHY management */
  30. #define CONFIG_PHY_ADDR 0 /* PHY address */
  31. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  32. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
  33. #undef CONFIG_HAS_ETH1
  34. #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
  35. /*
  36. * BOOTP options
  37. */
  38. #define CONFIG_BOOTP_SUBNETMASK
  39. #define CONFIG_BOOTP_GATEWAY
  40. #define CONFIG_BOOTP_HOSTNAME
  41. #define CONFIG_BOOTP_BOOTPATH
  42. #define CONFIG_BOOTP_DNS
  43. #define CONFIG_BOOTP_DNS2
  44. #define CONFIG_BOOTP_SEND_HOSTNAME
  45. /*
  46. * Command line configuration.
  47. */
  48. #define CONFIG_CMD_PCI
  49. #define CONFIG_SUPPORT_VFAT
  50. #undef CONFIG_WATCHDOG /* watchdog disabled */
  51. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  52. /*
  53. * Miscellaneous configurable options
  54. */
  55. #undef CONFIG_SYS_LONGHELP /* undef to save memory */
  56. #if defined(CONFIG_CMD_KGDB)
  57. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  58. #else
  59. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  60. #endif
  61. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  62. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  63. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  64. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  65. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  66. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  67. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  68. #define CONFIG_CONS_INDEX 1 /* Use UART0 */
  69. #define CONFIG_SYS_NS16550_SERIAL
  70. #define CONFIG_SYS_NS16550_REG_SIZE 1
  71. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  72. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  73. #define CONFIG_SYS_BASE_BAUD 691200
  74. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  75. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  76. #define CONFIG_CMDLINE_EDITING /* add command line history */
  77. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
  78. /*-----------------------------------------------------------------------
  79. * PCI stuff
  80. *-----------------------------------------------------------------------
  81. */
  82. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  83. #define PCI_HOST_FORCE 1 /* configure as pci host */
  84. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  85. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  86. #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
  87. /* resource configuration */
  88. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  89. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  90. #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  91. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  92. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  93. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
  94. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  95. #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
  96. #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
  97. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  98. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  99. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  100. #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
  101. #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
  102. /*-----------------------------------------------------------------------
  103. * IDE/ATA stuff
  104. *-----------------------------------------------------------------------
  105. */
  106. #undef CONFIG_IDE_LED /* no led for ide supported */
  107. #define CONFIG_IDE_RESET 1 /* reset for ide supported */
  108. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
  109. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
  110. #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
  111. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  112. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  113. #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
  114. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
  115. /*-----------------------------------------------------------------------
  116. * Start addresses for the final memory configuration
  117. * (Set up by the startup code)
  118. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  119. */
  120. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  121. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  122. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  123. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  124. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  125. #define CONFIG_PRAM 0 /* use pram variable to overwrite */
  126. /*
  127. * For booting Linux, the board info and command line data
  128. * have to be in the first 8 MB of memory, since this is
  129. * the maximum mapped by the Linux kernel during initialization.
  130. */
  131. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  132. /*-----------------------------------------------------------------------
  133. * FLASH organization
  134. */
  135. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  136. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  137. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  138. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  139. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  140. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  141. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  142. /*
  143. * The following defines are added for buggy IOP480 byte interface.
  144. * All other boards should use the standard values (CPCI405 etc.)
  145. */
  146. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  147. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  148. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  149. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  150. #if 0 /* Use NVRAM for environment variables */
  151. /*-----------------------------------------------------------------------
  152. * NVRAM organization
  153. */
  154. #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  155. #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
  156. #define CONFIG_ENV_ADDR \
  157. (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
  158. #else /* Use EEPROM for environment variables */
  159. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  160. #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
  161. #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
  162. /* total size of a CAT24WC16 is 2048 bytes */
  163. #endif
  164. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
  165. #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
  166. #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
  167. /*-----------------------------------------------------------------------
  168. * I2C EEPROM (CAT24WC16) for environment
  169. */
  170. #define CONFIG_SYS_I2C
  171. #define CONFIG_SYS_I2C_PPC4XX
  172. #define CONFIG_SYS_I2C_PPC4XX_CH0
  173. #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
  174. #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
  175. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  176. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  177. /* mask of address bits that overflow into the "EEPROM chip address" */
  178. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  179. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  180. /* 16 byte page write mode using*/
  181. /* last 4 bits of the address */
  182. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  183. /*
  184. * Init Memory Controller:
  185. *
  186. * BR0/1 and OR0/1 (FLASH)
  187. */
  188. #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
  189. #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
  190. /*-----------------------------------------------------------------------
  191. * External Bus Controller (EBC) Setup
  192. */
  193. /* Memory Bank 0 (Flash Bank 0) initialization */
  194. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  195. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  196. /* Memory Bank 1 (Flash Bank 1) initialization */
  197. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  198. #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
  199. /* Memory Bank 2 (CAN0, 1) initialization */
  200. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  201. #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  202. #define CONFIG_SYS_LED_ADDR 0xF0000380
  203. /* Memory Bank 3 (CompactFlash IDE) initialization */
  204. #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  205. #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  206. /* Memory Bank 4 (NVRAM/RTC) initialization */
  207. /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
  208. #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
  209. #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
  210. /* Memory Bank 5 (optional Quart) initialization */
  211. #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
  212. #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
  213. /* Memory Bank 6 (FPGA internal) initialization */
  214. #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  215. #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  216. #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
  217. /*-----------------------------------------------------------------------
  218. * FPGA stuff
  219. */
  220. /* FPGA internal regs */
  221. #define CONFIG_SYS_FPGA_MODE 0x00
  222. #define CONFIG_SYS_FPGA_STATUS 0x02
  223. #define CONFIG_SYS_FPGA_TS 0x04
  224. #define CONFIG_SYS_FPGA_TS_LOW 0x06
  225. #define CONFIG_SYS_FPGA_TS_CAP0 0x10
  226. #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
  227. #define CONFIG_SYS_FPGA_TS_CAP1 0x14
  228. #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
  229. #define CONFIG_SYS_FPGA_TS_CAP2 0x18
  230. #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
  231. #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
  232. #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
  233. /* FPGA Mode Reg */
  234. #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
  235. #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
  236. #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
  237. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
  238. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
  239. #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
  240. /* FPGA Status Reg */
  241. #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
  242. #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
  243. #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
  244. #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
  245. #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
  246. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  247. #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
  248. /* FPGA program pin configuration */
  249. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  250. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  251. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  252. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  253. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  254. /*-----------------------------------------------------------------------
  255. * Definitions for initial stack pointer and data area (in data cache)
  256. */
  257. #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
  258. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
  259. #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
  260. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  261. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  262. #endif /* __CONFIG_H */