4xx_enet.c 61 KB

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  1. /*
  2. * SPDX-License-Identifier: GPL-2.0 IBM-pibs
  3. */
  4. /*-----------------------------------------------------------------------------+
  5. *
  6. * File Name: enetemac.c
  7. *
  8. * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
  9. *
  10. * Author: Mark Wisner
  11. *
  12. * Change Activity-
  13. *
  14. * Date Description of Change BY
  15. * --------- --------------------- ---
  16. * 05-May-99 Created MKW
  17. * 27-Jun-99 Clean up JWB
  18. * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
  19. * 29-Jul-99 Added Full duplex support MKW
  20. * 06-Aug-99 Changed names for Mal CR reg MKW
  21. * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
  22. * 24-Aug-99 Marked descriptor empty after call_xlc MKW
  23. * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
  24. * to avoid chaining maximum sized packets. Push starting
  25. * RX descriptor address up to the next cache line boundary.
  26. * 16-Jan-00 Added support for booting with IP of 0x0 MKW
  27. * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
  28. * EMAC0_RXM register. JWB
  29. * 12-Mar-01 anne-sophie.harnois@nextream.fr
  30. * - Variables are compatible with those already defined in
  31. * include/net.h
  32. * - Receive buffer descriptor ring is used to send buffers
  33. * to the user
  34. * - Info print about send/received/handled packet number if
  35. * INFO_405_ENET is set
  36. * 17-Apr-01 stefan.roese@esd-electronics.com
  37. * - MAL reset in "eth_halt" included
  38. * - Enet speed and duplex output now in one line
  39. * 08-May-01 stefan.roese@esd-electronics.com
  40. * - MAL error handling added (eth_init called again)
  41. * 13-Nov-01 stefan.roese@esd-electronics.com
  42. * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
  43. * 04-Jan-02 stefan.roese@esd-electronics.com
  44. * - Wait for PHY auto negotiation to complete added
  45. * 06-Feb-02 stefan.roese@esd-electronics.com
  46. * - Bug fixed in waiting for auto negotiation to complete
  47. * 26-Feb-02 stefan.roese@esd-electronics.com
  48. * - rx and tx buffer descriptors now allocated (no fixed address
  49. * used anymore)
  50. * 17-Jun-02 stefan.roese@esd-electronics.com
  51. * - MAL error debug printf 'M' removed (rx de interrupt may
  52. * occur upon many incoming packets with only 4 rx buffers).
  53. *-----------------------------------------------------------------------------*
  54. * 17-Nov-03 travis.sawyer@sandburst.com
  55. * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
  56. * in the 440GX. This port should work with the 440GP
  57. * (2 EMACs) also
  58. * 15-Aug-05 sr@denx.de
  59. * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
  60. now handling all 4xx cpu's.
  61. *-----------------------------------------------------------------------------*/
  62. #include <config.h>
  63. #include <common.h>
  64. #include <net.h>
  65. #include <asm/processor.h>
  66. #include <asm/io.h>
  67. #include <asm/cache.h>
  68. #include <asm/mmu.h>
  69. #include <asm/ppc4xx.h>
  70. #include <asm/ppc4xx-emac.h>
  71. #include <asm/ppc4xx-mal.h>
  72. #include <miiphy.h>
  73. #include <malloc.h>
  74. #include <linux/compiler.h>
  75. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  76. #error "CONFIG_MII has to be defined!"
  77. #endif
  78. #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
  79. #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
  80. /* Ethernet Transmit and Receive Buffers */
  81. /* AS.HARNOIS
  82. * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
  83. * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
  84. */
  85. #define ENET_MAX_MTU PKTSIZE
  86. #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
  87. /*-----------------------------------------------------------------------------+
  88. * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
  89. * Interrupt Controller).
  90. *-----------------------------------------------------------------------------*/
  91. #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
  92. #if defined(CONFIG_HAS_ETH3)
  93. #if !defined(CONFIG_440GX)
  94. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  95. UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  96. #else
  97. /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
  98. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  99. #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
  100. #endif /* !defined(CONFIG_440GX) */
  101. #elif defined(CONFIG_HAS_ETH2)
  102. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
  103. UIC_MASK(ETH_IRQ_NUM(2)))
  104. #elif defined(CONFIG_HAS_ETH1)
  105. #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
  106. #else
  107. #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
  108. #endif
  109. /*
  110. * Define a default version for UIC_ETHxB for non 440GX so that we can
  111. * use common code for all 4xx variants
  112. */
  113. #if !defined(UIC_ETHxB)
  114. #define UIC_ETHxB 0
  115. #endif
  116. #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
  117. #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
  118. #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
  119. #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
  120. #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
  121. #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
  122. #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
  123. /*
  124. * We have 3 different interrupt types:
  125. * - MAL interrupts indicating successful transfer
  126. * - MAL error interrupts indicating MAL related errors
  127. * - EMAC interrupts indicating EMAC related errors
  128. *
  129. * All those interrupts can be on different UIC's, but since
  130. * now at least all interrupts from one type are on the same
  131. * UIC. Only exception is 440GX where the EMAC interrupts are
  132. * spread over two UIC's!
  133. */
  134. #if defined(CONFIG_440GX)
  135. #define UIC_BASE_MAL UIC1_DCR_BASE
  136. #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
  137. #define UIC_BASE_EMAC UIC2_DCR_BASE
  138. #define UIC_BASE_EMAC_B UIC3_DCR_BASE
  139. #else
  140. #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
  141. #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
  142. #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  143. #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
  144. #endif
  145. #undef INFO_4XX_ENET
  146. #define BI_PHYMODE_NONE 0
  147. #define BI_PHYMODE_ZMII 1
  148. #define BI_PHYMODE_RGMII 2
  149. #define BI_PHYMODE_GMII 3
  150. #define BI_PHYMODE_RTBI 4
  151. #define BI_PHYMODE_TBI 5
  152. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  153. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  154. defined(CONFIG_405EX)
  155. #define BI_PHYMODE_SMII 6
  156. #define BI_PHYMODE_MII 7
  157. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  158. #define BI_PHYMODE_RMII 8
  159. #endif
  160. #endif
  161. #define BI_PHYMODE_SGMII 9
  162. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  163. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  164. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  165. defined(CONFIG_405EX)
  166. #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
  167. #endif
  168. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  169. #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
  170. #endif
  171. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  172. #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
  173. #else
  174. #define MAL_RX_CHAN_MUL 1
  175. #endif
  176. /*--------------------------------------------------------------------+
  177. * Fixed PHY (PHY-less) support for Ethernet Ports.
  178. *--------------------------------------------------------------------*/
  179. /*
  180. * Some boards do not have a PHY for each ethernet port. These ports
  181. * are known as Fixed PHY (or PHY-less) ports. For such ports, set
  182. * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
  183. * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
  184. * duplex should be for these ports in the board configuration
  185. * file.
  186. *
  187. * For Example:
  188. * #define CONFIG_FIXED_PHY 0xFFFFFFFF
  189. *
  190. * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
  191. * #define CONFIG_PHY1_ADDR 1
  192. * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
  193. * #define CONFIG_PHY3_ADDR 3
  194. *
  195. * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
  196. * {devnum, speed, duplex},
  197. *
  198. * #define CONFIG_SYS_FIXED_PHY_PORTS \
  199. * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
  200. * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
  201. */
  202. #ifndef CONFIG_FIXED_PHY
  203. #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
  204. #endif
  205. #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  206. #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
  207. #endif
  208. struct fixed_phy_port {
  209. unsigned int devnum; /* ethernet port */
  210. unsigned int speed; /* specified speed 10,100 or 1000 */
  211. unsigned int duplex; /* specified duplex FULL or HALF */
  212. };
  213. static const struct fixed_phy_port fixed_phy_port[] = {
  214. CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  215. };
  216. /*-----------------------------------------------------------------------------+
  217. * Global variables. TX and RX descriptors and buffers.
  218. *-----------------------------------------------------------------------------*/
  219. /*
  220. * Get count of EMAC devices (doesn't have to be the max. possible number
  221. * supported by the cpu)
  222. *
  223. * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
  224. * EMAC count is possible. As it is needed for the Kilauea/Haleakala
  225. * 405EX/405EXr eval board, using the same binary.
  226. */
  227. #if defined(CONFIG_BOARD_EMAC_COUNT)
  228. #define LAST_EMAC_NUM board_emac_count()
  229. #else /* CONFIG_BOARD_EMAC_COUNT */
  230. #if defined(CONFIG_HAS_ETH3)
  231. #define LAST_EMAC_NUM 4
  232. #elif defined(CONFIG_HAS_ETH2)
  233. #define LAST_EMAC_NUM 3
  234. #elif defined(CONFIG_HAS_ETH1)
  235. #define LAST_EMAC_NUM 2
  236. #else
  237. #define LAST_EMAC_NUM 1
  238. #endif
  239. #endif /* CONFIG_BOARD_EMAC_COUNT */
  240. /* normal boards start with EMAC0 */
  241. #if !defined(CONFIG_EMAC_NR_START)
  242. #define CONFIG_EMAC_NR_START 0
  243. #endif
  244. #define MAL_RX_DESC_SIZE 2048
  245. #define MAL_TX_DESC_SIZE 2048
  246. #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
  247. /*-----------------------------------------------------------------------------+
  248. * Prototypes and externals.
  249. *-----------------------------------------------------------------------------*/
  250. static void enet_rcv (struct eth_device *dev, unsigned long malisr);
  251. int enetInt (struct eth_device *dev);
  252. static void mal_err (struct eth_device *dev, unsigned long isr,
  253. unsigned long uic, unsigned long maldef,
  254. unsigned long mal_errr);
  255. static void emac_err (struct eth_device *dev, unsigned long isr);
  256. extern int phy_setup_aneg (char *devname, unsigned char addr);
  257. int emac4xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  258. int emac4xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  259. u16 value);
  260. int board_emac_count(void);
  261. static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
  262. {
  263. #if defined(CONFIG_440SPE) || \
  264. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  265. defined(CONFIG_405EX)
  266. u32 val;
  267. mfsdr(SDR0_MFR, val);
  268. val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  269. mtsdr(SDR0_MFR, val);
  270. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  271. u32 val;
  272. mfsdr(SDR0_ETH_CFG, val);
  273. val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  274. mtsdr(SDR0_ETH_CFG, val);
  275. #endif
  276. }
  277. static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
  278. {
  279. #if defined(CONFIG_440SPE) || \
  280. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  281. defined(CONFIG_405EX)
  282. u32 val;
  283. mfsdr(SDR0_MFR, val);
  284. val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
  285. mtsdr(SDR0_MFR, val);
  286. #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
  287. u32 val;
  288. mfsdr(SDR0_ETH_CFG, val);
  289. val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
  290. mtsdr(SDR0_ETH_CFG, val);
  291. #endif
  292. }
  293. /*-----------------------------------------------------------------------------+
  294. | ppc_4xx_eth_halt
  295. | Disable MAL channel, and EMACn
  296. +-----------------------------------------------------------------------------*/
  297. static void ppc_4xx_eth_halt (struct eth_device *dev)
  298. {
  299. EMAC_4XX_HW_PST hw_p = dev->priv;
  300. u32 val = 10000;
  301. out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
  302. /* 1st reset MAL channel */
  303. /* Note: writing a 0 to a channel has no effect */
  304. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  305. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
  306. #else
  307. mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  308. #endif
  309. mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
  310. /* wait for reset */
  311. while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
  312. udelay (1000); /* Delay 1 MS so as not to hammer the register */
  313. val--;
  314. if (val == 0)
  315. break;
  316. }
  317. /* provide clocks for EMAC internal loopback */
  318. emac_loopback_enable(hw_p);
  319. /* EMAC RESET */
  320. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  321. /* remove clocks for EMAC internal loopback */
  322. emac_loopback_disable(hw_p);
  323. #ifndef CONFIG_NETCONSOLE
  324. hw_p->print_speed = 1; /* print speed message again next time */
  325. #endif
  326. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  327. /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
  328. mfsdr(SDR0_ETH_CFG, val);
  329. val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  330. mtsdr(SDR0_ETH_CFG, val);
  331. #endif
  332. return;
  333. }
  334. #if defined (CONFIG_440GX)
  335. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  336. {
  337. unsigned long pfc1;
  338. unsigned long zmiifer;
  339. unsigned long rmiifer;
  340. mfsdr(SDR0_PFC1, pfc1);
  341. pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
  342. zmiifer = 0;
  343. rmiifer = 0;
  344. switch (pfc1) {
  345. case 1:
  346. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  347. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  348. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  349. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  350. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  351. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  352. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  353. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  354. break;
  355. case 2:
  356. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  357. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  358. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  359. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  360. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  361. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  362. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  363. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  364. break;
  365. case 3:
  366. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  367. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  368. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  369. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  370. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  371. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  372. break;
  373. case 4:
  374. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  375. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  376. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
  377. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
  378. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  379. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  380. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  381. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  382. break;
  383. case 5:
  384. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  385. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  386. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
  387. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  388. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  389. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  390. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  391. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  392. break;
  393. case 6:
  394. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  395. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  396. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  397. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  398. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  399. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  400. break;
  401. case 0:
  402. default:
  403. zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
  404. rmiifer = 0x0;
  405. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  406. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  407. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  408. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  409. break;
  410. }
  411. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  412. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  413. out_be32((void *)ZMII0_FER, zmiifer);
  414. out_be32((void *)RGMII_FER, rmiifer);
  415. return ((int)pfc1);
  416. }
  417. #endif /* CONFIG_440_GX */
  418. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  419. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  420. {
  421. unsigned long zmiifer=0x0;
  422. unsigned long pfc1;
  423. mfsdr(SDR0_PFC1, pfc1);
  424. pfc1 &= SDR0_PFC1_SELECT_MASK;
  425. switch (pfc1) {
  426. case SDR0_PFC1_SELECT_CONFIG_2:
  427. /* 1 x GMII port */
  428. out_be32((void *)ZMII0_FER, 0x00);
  429. out_be32((void *)RGMII_FER, 0x00000037);
  430. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  431. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  432. break;
  433. case SDR0_PFC1_SELECT_CONFIG_4:
  434. /* 2 x RGMII ports */
  435. out_be32((void *)ZMII0_FER, 0x00);
  436. out_be32((void *)RGMII_FER, 0x00000055);
  437. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  438. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  439. break;
  440. case SDR0_PFC1_SELECT_CONFIG_6:
  441. /* 2 x SMII ports */
  442. out_be32((void *)ZMII0_FER,
  443. ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
  444. ((ZMII_FER_SMII) << ZMII_FER_V(1)));
  445. out_be32((void *)RGMII_FER, 0x00000000);
  446. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  447. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  448. break;
  449. case SDR0_PFC1_SELECT_CONFIG_1_2:
  450. /* only 1 x MII supported */
  451. out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
  452. out_be32((void *)RGMII_FER, 0x00000000);
  453. bis->bi_phymode[0] = BI_PHYMODE_MII;
  454. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  455. break;
  456. default:
  457. break;
  458. }
  459. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  460. zmiifer = in_be32((void *)ZMII0_FER);
  461. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  462. out_be32((void *)ZMII0_FER, zmiifer);
  463. return ((int)0x0);
  464. }
  465. #endif /* CONFIG_440EPX */
  466. #if defined(CONFIG_405EX)
  467. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  468. {
  469. u32 rgmiifer = 0;
  470. /*
  471. * The 405EX(r)'s RGMII bridge can operate in one of several
  472. * modes, only one of which (2 x RGMII) allows the
  473. * simultaneous use of both EMACs on the 405EX.
  474. */
  475. switch (CONFIG_EMAC_PHY_MODE) {
  476. case EMAC_PHY_MODE_NONE:
  477. /* No ports */
  478. rgmiifer |= RGMII_FER_DIS << 0;
  479. rgmiifer |= RGMII_FER_DIS << 4;
  480. out_be32((void *)RGMII_FER, rgmiifer);
  481. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  482. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  483. break;
  484. case EMAC_PHY_MODE_NONE_RGMII:
  485. /* 1 x RGMII port on channel 0 */
  486. rgmiifer |= RGMII_FER_RGMII << 0;
  487. rgmiifer |= RGMII_FER_DIS << 4;
  488. out_be32((void *)RGMII_FER, rgmiifer);
  489. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  490. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  491. break;
  492. case EMAC_PHY_MODE_RGMII_NONE:
  493. /* 1 x RGMII port on channel 1 */
  494. rgmiifer |= RGMII_FER_DIS << 0;
  495. rgmiifer |= RGMII_FER_RGMII << 4;
  496. out_be32((void *)RGMII_FER, rgmiifer);
  497. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  498. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  499. break;
  500. case EMAC_PHY_MODE_RGMII_RGMII:
  501. /* 2 x RGMII ports */
  502. rgmiifer |= RGMII_FER_RGMII << 0;
  503. rgmiifer |= RGMII_FER_RGMII << 4;
  504. out_be32((void *)RGMII_FER, rgmiifer);
  505. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  506. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  507. break;
  508. case EMAC_PHY_MODE_NONE_GMII:
  509. /* 1 x GMII port on channel 0 */
  510. rgmiifer |= RGMII_FER_GMII << 0;
  511. rgmiifer |= RGMII_FER_DIS << 4;
  512. out_be32((void *)RGMII_FER, rgmiifer);
  513. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  514. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  515. break;
  516. case EMAC_PHY_MODE_NONE_MII:
  517. /* 1 x MII port on channel 0 */
  518. rgmiifer |= RGMII_FER_MII << 0;
  519. rgmiifer |= RGMII_FER_DIS << 4;
  520. out_be32((void *)RGMII_FER, rgmiifer);
  521. bis->bi_phymode[0] = BI_PHYMODE_MII;
  522. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  523. break;
  524. case EMAC_PHY_MODE_GMII_NONE:
  525. /* 1 x GMII port on channel 1 */
  526. rgmiifer |= RGMII_FER_DIS << 0;
  527. rgmiifer |= RGMII_FER_GMII << 4;
  528. out_be32((void *)RGMII_FER, rgmiifer);
  529. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  530. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  531. break;
  532. case EMAC_PHY_MODE_MII_NONE:
  533. /* 1 x MII port on channel 1 */
  534. rgmiifer |= RGMII_FER_DIS << 0;
  535. rgmiifer |= RGMII_FER_MII << 4;
  536. out_be32((void *)RGMII_FER, rgmiifer);
  537. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  538. bis->bi_phymode[1] = BI_PHYMODE_MII;
  539. break;
  540. default:
  541. break;
  542. }
  543. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  544. rgmiifer = in_be32((void *)RGMII_FER);
  545. rgmiifer |= (1 << (19-devnum));
  546. out_be32((void *)RGMII_FER, rgmiifer);
  547. return ((int)0x0);
  548. }
  549. #endif /* CONFIG_405EX */
  550. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  551. int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
  552. {
  553. u32 eth_cfg;
  554. u32 zmiifer; /* ZMII0_FER reg. */
  555. u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
  556. u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
  557. int mode;
  558. zmiifer = 0;
  559. rmiifer = 0;
  560. rmiifer1 = 0;
  561. #if defined(CONFIG_460EX)
  562. mode = 9;
  563. mfsdr(SDR0_ETH_CFG, eth_cfg);
  564. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  565. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
  566. mode = 11; /* config SGMII */
  567. #else
  568. mode = 10;
  569. mfsdr(SDR0_ETH_CFG, eth_cfg);
  570. if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
  571. ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
  572. ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
  573. mode = 12; /* config SGMII */
  574. #endif
  575. /* TODO:
  576. * NOTE: 460GT has 2 RGMII bridge cores:
  577. * emac0 ------ RGMII0_BASE
  578. * |
  579. * emac1 -----+
  580. *
  581. * emac2 ------ RGMII1_BASE
  582. * |
  583. * emac3 -----+
  584. *
  585. * 460EX has 1 RGMII bridge core:
  586. * and RGMII1_BASE is disabled
  587. * emac0 ------ RGMII0_BASE
  588. * |
  589. * emac1 -----+
  590. */
  591. /*
  592. * Right now only 2*RGMII is supported. Please extend when needed.
  593. * sr - 2008-02-19
  594. * Add SGMII support.
  595. * vg - 2008-07-28
  596. */
  597. switch (mode) {
  598. case 1:
  599. /* 1 MII - 460EX */
  600. /* GMC0 EMAC4_0, ZMII Bridge */
  601. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  602. bis->bi_phymode[0] = BI_PHYMODE_MII;
  603. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  604. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  605. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  606. break;
  607. case 2:
  608. /* 2 MII - 460GT */
  609. /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
  610. zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
  611. zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
  612. bis->bi_phymode[0] = BI_PHYMODE_MII;
  613. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  614. bis->bi_phymode[2] = BI_PHYMODE_MII;
  615. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  616. break;
  617. case 3:
  618. /* 2 RMII - 460EX */
  619. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  620. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  621. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  622. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  623. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  624. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  625. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  626. break;
  627. case 4:
  628. /* 4 RMII - 460GT */
  629. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
  630. /* ZMII Bridge */
  631. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  632. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  633. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  634. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  635. bis->bi_phymode[0] = BI_PHYMODE_RMII;
  636. bis->bi_phymode[1] = BI_PHYMODE_RMII;
  637. bis->bi_phymode[2] = BI_PHYMODE_RMII;
  638. bis->bi_phymode[3] = BI_PHYMODE_RMII;
  639. break;
  640. case 5:
  641. /* 2 SMII - 460EX */
  642. /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
  643. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  644. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  645. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  646. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  647. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  648. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  649. break;
  650. case 6:
  651. /* 4 SMII - 460GT */
  652. /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
  653. /* ZMII Bridge */
  654. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  655. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  656. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
  657. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
  658. bis->bi_phymode[0] = BI_PHYMODE_SMII;
  659. bis->bi_phymode[1] = BI_PHYMODE_SMII;
  660. bis->bi_phymode[2] = BI_PHYMODE_SMII;
  661. bis->bi_phymode[3] = BI_PHYMODE_SMII;
  662. break;
  663. case 7:
  664. /* This is the default mode that we want for board bringup - Maple */
  665. /* 1 GMII - 460EX */
  666. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  667. rmiifer |= RGMII_FER_MDIO(0);
  668. if (devnum == 0) {
  669. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  670. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  671. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  672. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  673. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  674. } else {
  675. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
  676. bis->bi_phymode[0] = BI_PHYMODE_NONE;
  677. bis->bi_phymode[1] = BI_PHYMODE_GMII;
  678. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  679. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  680. }
  681. break;
  682. case 8:
  683. /* 2 GMII - 460GT */
  684. /* GMC0 EMAC4_0, RGMII Bridge 0 */
  685. /* GMC1 EMAC4_2, RGMII Bridge 1 */
  686. rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
  687. rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
  688. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  689. rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
  690. bis->bi_phymode[0] = BI_PHYMODE_GMII;
  691. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  692. bis->bi_phymode[2] = BI_PHYMODE_GMII;
  693. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  694. break;
  695. case 9:
  696. /* 2 RGMII - 460EX */
  697. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  698. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  699. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  700. rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
  701. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  702. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  703. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  704. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  705. break;
  706. case 10:
  707. /* 4 RGMII - 460GT */
  708. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  709. /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
  710. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  711. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  712. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
  713. rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
  714. bis->bi_phymode[0] = BI_PHYMODE_RGMII;
  715. bis->bi_phymode[1] = BI_PHYMODE_RGMII;
  716. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  717. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  718. break;
  719. case 11:
  720. /* 2 SGMII - 460EX */
  721. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  722. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  723. bis->bi_phymode[2] = BI_PHYMODE_NONE;
  724. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  725. break;
  726. case 12:
  727. /* 3 SGMII - 460GT */
  728. bis->bi_phymode[0] = BI_PHYMODE_SGMII;
  729. bis->bi_phymode[1] = BI_PHYMODE_SGMII;
  730. bis->bi_phymode[2] = BI_PHYMODE_SGMII;
  731. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  732. break;
  733. default:
  734. break;
  735. }
  736. /* Set EMAC for MDIO */
  737. mfsdr(SDR0_ETH_CFG, eth_cfg);
  738. eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
  739. mtsdr(SDR0_ETH_CFG, eth_cfg);
  740. out_be32((void *)RGMII_FER, rmiifer);
  741. #if defined(CONFIG_460GT)
  742. out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
  743. #endif
  744. /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
  745. mfsdr(SDR0_ETH_CFG, eth_cfg);
  746. eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  747. mtsdr(SDR0_ETH_CFG, eth_cfg);
  748. return 0;
  749. }
  750. #endif /* CONFIG_460EX || CONFIG_460GT */
  751. static inline void *malloc_aligned(u32 size, u32 align)
  752. {
  753. return (void *)(((u32)malloc(size + align) + align - 1) &
  754. ~(align - 1));
  755. }
  756. static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
  757. {
  758. int i;
  759. unsigned long reg = 0;
  760. unsigned long msr;
  761. unsigned long speed;
  762. unsigned long duplex;
  763. unsigned long failsafe;
  764. unsigned mode_reg;
  765. unsigned short devnum;
  766. unsigned short reg_short;
  767. #if defined(CONFIG_440GX) || \
  768. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  769. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  770. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  771. defined(CONFIG_405EX)
  772. u32 opbfreq;
  773. sys_info_t sysinfo;
  774. #if defined(CONFIG_440GX) || \
  775. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  776. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  777. defined(CONFIG_405EX)
  778. __maybe_unused int ethgroup = -1;
  779. #endif
  780. #endif
  781. u32 bd_cached;
  782. u32 bd_uncached = 0;
  783. #ifdef CONFIG_4xx_DCACHE
  784. static u32 last_used_ea = 0;
  785. #endif
  786. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  787. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  788. defined(CONFIG_405EX)
  789. int rgmii_channel;
  790. #endif
  791. EMAC_4XX_HW_PST hw_p = dev->priv;
  792. /* before doing anything, figure out if we have a MAC address */
  793. /* if not, bail */
  794. if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
  795. printf("ERROR: ethaddr not set!\n");
  796. return -1;
  797. }
  798. #if defined(CONFIG_440GX) || \
  799. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  800. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  801. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  802. defined(CONFIG_405EX)
  803. /* Need to get the OPB frequency so we can access the PHY */
  804. get_sys_info (&sysinfo);
  805. #endif
  806. msr = mfmsr ();
  807. mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
  808. devnum = hw_p->devnum;
  809. #ifdef INFO_4XX_ENET
  810. /* AS.HARNOIS
  811. * We should have :
  812. * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
  813. * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
  814. * is possible that new packets (without relationship with
  815. * current transfer) have got the time to arrived before
  816. * netloop calls eth_halt
  817. */
  818. printf ("About preceding transfer (eth%d):\n"
  819. "- Sent packet number %d\n"
  820. "- Received packet number %d\n"
  821. "- Handled packet number %d\n",
  822. hw_p->devnum,
  823. hw_p->stats.pkts_tx,
  824. hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
  825. hw_p->stats.pkts_tx = 0;
  826. hw_p->stats.pkts_rx = 0;
  827. hw_p->stats.pkts_handled = 0;
  828. hw_p->print_speed = 1; /* print speed message again next time */
  829. #endif
  830. hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
  831. hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
  832. hw_p->rx_slot = 0; /* MAL Receive Slot */
  833. hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
  834. hw_p->rx_u_index = 0; /* Receive User Queue Index */
  835. hw_p->tx_slot = 0; /* MAL Transmit Slot */
  836. hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
  837. hw_p->tx_u_index = 0; /* Transmit User Queue Index */
  838. #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
  839. /* set RMII mode */
  840. /* NOTE: 440GX spec states that mode is mutually exclusive */
  841. /* NOTE: Therefore, disable all other EMACS, since we handle */
  842. /* NOTE: only one emac at a time */
  843. reg = 0;
  844. out_be32((void *)ZMII0_FER, 0);
  845. udelay (100);
  846. #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  847. out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
  848. #elif defined(CONFIG_440GX) || \
  849. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  850. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  851. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  852. #endif
  853. out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
  854. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  855. #if defined(CONFIG_405EX)
  856. ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
  857. #endif
  858. sync();
  859. /* provide clocks for EMAC internal loopback */
  860. emac_loopback_enable(hw_p);
  861. /* EMAC RESET */
  862. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
  863. /* remove clocks for EMAC internal loopback */
  864. emac_loopback_disable(hw_p);
  865. failsafe = 1000;
  866. while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
  867. udelay (1000);
  868. failsafe--;
  869. }
  870. if (failsafe <= 0)
  871. printf("\nProblem resetting EMAC!\n");
  872. #if defined(CONFIG_440GX) || \
  873. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  874. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  875. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  876. defined(CONFIG_405EX)
  877. /* Whack the M1 register */
  878. mode_reg = 0x0;
  879. mode_reg &= ~0x00000038;
  880. opbfreq = sysinfo.freqOPB / 1000000;
  881. if (opbfreq <= 50);
  882. else if (opbfreq <= 66)
  883. mode_reg |= EMAC_MR1_OBCI_66;
  884. else if (opbfreq <= 83)
  885. mode_reg |= EMAC_MR1_OBCI_83;
  886. else if (opbfreq <= 100)
  887. mode_reg |= EMAC_MR1_OBCI_100;
  888. else
  889. mode_reg |= EMAC_MR1_OBCI_GT100;
  890. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  891. #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
  892. #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
  893. defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
  894. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  895. /*
  896. * In SGMII mode, GPCS access is needed for
  897. * communication with the internal SGMII SerDes.
  898. */
  899. switch (devnum) {
  900. #if defined(CONFIG_GPCS_PHY_ADDR)
  901. case 0:
  902. reg = CONFIG_GPCS_PHY_ADDR;
  903. break;
  904. #endif
  905. #if defined(CONFIG_GPCS_PHY1_ADDR)
  906. case 1:
  907. reg = CONFIG_GPCS_PHY1_ADDR;
  908. break;
  909. #endif
  910. #if defined(CONFIG_GPCS_PHY2_ADDR)
  911. case 2:
  912. reg = CONFIG_GPCS_PHY2_ADDR;
  913. break;
  914. #endif
  915. #if defined(CONFIG_GPCS_PHY3_ADDR)
  916. case 3:
  917. reg = CONFIG_GPCS_PHY3_ADDR;
  918. break;
  919. #endif
  920. }
  921. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  922. mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
  923. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  924. /* Configure GPCS interface to recommended setting for SGMII */
  925. miiphy_reset(dev->name, reg);
  926. miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
  927. miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
  928. miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
  929. }
  930. #endif /* defined(CONFIG_GPCS_PHY_ADDR) */
  931. /* wait for PHY to complete auto negotiation */
  932. reg_short = 0;
  933. switch (devnum) {
  934. case 0:
  935. reg = CONFIG_PHY_ADDR;
  936. break;
  937. #if defined (CONFIG_PHY1_ADDR)
  938. case 1:
  939. reg = CONFIG_PHY1_ADDR;
  940. break;
  941. #endif
  942. #if defined (CONFIG_PHY2_ADDR)
  943. case 2:
  944. reg = CONFIG_PHY2_ADDR;
  945. break;
  946. #endif
  947. #if defined (CONFIG_PHY3_ADDR)
  948. case 3:
  949. reg = CONFIG_PHY3_ADDR;
  950. break;
  951. #endif
  952. default:
  953. reg = CONFIG_PHY_ADDR;
  954. break;
  955. }
  956. bis->bi_phynum[devnum] = reg;
  957. if (reg == CONFIG_FIXED_PHY)
  958. goto get_speed;
  959. #if defined(CONFIG_PHY_RESET)
  960. /*
  961. * Reset the phy, only if its the first time through
  962. * otherwise, just check the speeds & feeds
  963. */
  964. if (hw_p->first_init == 0) {
  965. #if defined(CONFIG_M88E1111_PHY)
  966. miiphy_write (dev->name, reg, 0x14, 0x0ce3);
  967. miiphy_write (dev->name, reg, 0x18, 0x4101);
  968. miiphy_write (dev->name, reg, 0x09, 0x0e00);
  969. miiphy_write (dev->name, reg, 0x04, 0x01e1);
  970. #if defined(CONFIG_M88E1111_DISABLE_FIBER)
  971. miiphy_read(dev->name, reg, 0x1b, &reg_short);
  972. reg_short |= 0x8000;
  973. miiphy_write(dev->name, reg, 0x1b, reg_short);
  974. #endif
  975. #endif
  976. #if defined(CONFIG_M88E1112_PHY)
  977. if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
  978. /*
  979. * Marvell 88E1112 PHY needs to have the SGMII MAC
  980. * interace (page 2) properly configured to
  981. * communicate with the 460EX/GT GPCS interface.
  982. */
  983. /* Set access to Page 2 */
  984. miiphy_write(dev->name, reg, 0x16, 0x0002);
  985. miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
  986. miiphy_read(dev->name, reg, 0x1a, &reg_short);
  987. reg_short |= 0x8000; /* bypass Auto-Negotiation */
  988. miiphy_write(dev->name, reg, 0x1a, reg_short);
  989. miiphy_reset(dev->name, reg); /* reset MAC interface */
  990. /* Reset access to Page 0 */
  991. miiphy_write(dev->name, reg, 0x16, 0x0000);
  992. }
  993. #endif /* defined(CONFIG_M88E1112_PHY) */
  994. miiphy_reset (dev->name, reg);
  995. #if defined(CONFIG_440GX) || \
  996. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  997. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  998. defined(CONFIG_405EX)
  999. #if defined(CONFIG_CIS8201_PHY)
  1000. /*
  1001. * Cicada 8201 PHY needs to have an extended register whacked
  1002. * for RGMII mode.
  1003. */
  1004. if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
  1005. #if defined(CONFIG_CIS8201_SHORT_ETCH)
  1006. miiphy_write (dev->name, reg, 23, 0x1300);
  1007. #else
  1008. miiphy_write (dev->name, reg, 23, 0x1000);
  1009. #endif
  1010. /*
  1011. * Vitesse VSC8201/Cicada CIS8201 errata:
  1012. * Interoperability problem with Intel 82547EI phys
  1013. * This work around (provided by Vitesse) changes
  1014. * the default timer convergence from 8ms to 12ms
  1015. */
  1016. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1017. miiphy_write (dev->name, reg, 0x08, 0x0200);
  1018. miiphy_write (dev->name, reg, 0x1f, 0x52b5);
  1019. miiphy_write (dev->name, reg, 0x02, 0x0004);
  1020. miiphy_write (dev->name, reg, 0x01, 0x0671);
  1021. miiphy_write (dev->name, reg, 0x00, 0x8fae);
  1022. miiphy_write (dev->name, reg, 0x1f, 0x2a30);
  1023. miiphy_write (dev->name, reg, 0x08, 0x0000);
  1024. miiphy_write (dev->name, reg, 0x1f, 0x0000);
  1025. /* end Vitesse/Cicada errata */
  1026. }
  1027. #endif /* defined(CONFIG_CIS8201_PHY) */
  1028. #if defined(CONFIG_ET1011C_PHY)
  1029. /*
  1030. * Agere ET1011c PHY needs to have an extended register whacked
  1031. * for RGMII mode.
  1032. */
  1033. if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
  1034. miiphy_read (dev->name, reg, 0x16, &reg_short);
  1035. reg_short &= ~(0x7);
  1036. reg_short |= 0x6; /* RGMII DLL Delay*/
  1037. miiphy_write (dev->name, reg, 0x16, reg_short);
  1038. miiphy_read (dev->name, reg, 0x17, &reg_short);
  1039. reg_short &= ~(0x40);
  1040. miiphy_write (dev->name, reg, 0x17, reg_short);
  1041. miiphy_write(dev->name, reg, 0x1c, 0x74f0);
  1042. }
  1043. #endif /* defined(CONFIG_ET1011C_PHY) */
  1044. #endif /* defined(CONFIG_440GX) ... */
  1045. /* Start/Restart autonegotiation */
  1046. phy_setup_aneg (dev->name, reg);
  1047. udelay (1000);
  1048. }
  1049. #endif /* defined(CONFIG_PHY_RESET) */
  1050. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1051. /*
  1052. * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
  1053. */
  1054. if ((reg_short & BMSR_ANEGCAPABLE)
  1055. && !(reg_short & BMSR_ANEGCOMPLETE)) {
  1056. puts ("Waiting for PHY auto negotiation to complete");
  1057. i = 0;
  1058. while (!(reg_short & BMSR_ANEGCOMPLETE)) {
  1059. /*
  1060. * Timeout reached ?
  1061. */
  1062. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  1063. puts (" TIMEOUT !\n");
  1064. break;
  1065. }
  1066. if ((i++ % 1000) == 0) {
  1067. putc ('.');
  1068. }
  1069. udelay (1000); /* 1 ms */
  1070. miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
  1071. }
  1072. puts (" done\n");
  1073. udelay (500000); /* another 500 ms (results in faster booting) */
  1074. }
  1075. get_speed:
  1076. if (reg == CONFIG_FIXED_PHY) {
  1077. for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
  1078. if (devnum == fixed_phy_port[i].devnum) {
  1079. speed = fixed_phy_port[i].speed;
  1080. duplex = fixed_phy_port[i].duplex;
  1081. break;
  1082. }
  1083. }
  1084. if (i == ARRAY_SIZE(fixed_phy_port)) {
  1085. printf("ERROR: PHY (%s) not configured correctly!\n",
  1086. dev->name);
  1087. return -1;
  1088. }
  1089. } else {
  1090. speed = miiphy_speed(dev->name, reg);
  1091. duplex = miiphy_duplex(dev->name, reg);
  1092. }
  1093. if (hw_p->print_speed) {
  1094. hw_p->print_speed = 0;
  1095. printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
  1096. (int) speed, (duplex == HALF) ? "HALF" : "FULL",
  1097. hw_p->devnum);
  1098. }
  1099. #if defined(CONFIG_440) && \
  1100. !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
  1101. !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
  1102. !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
  1103. #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1104. mfsdr(SDR0_MFR, reg);
  1105. if (speed == 100) {
  1106. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
  1107. } else {
  1108. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  1109. }
  1110. mtsdr(SDR0_MFR, reg);
  1111. #endif
  1112. /* Set ZMII/RGMII speed according to the phy link speed */
  1113. reg = in_be32((void *)ZMII0_SSR);
  1114. if ( (speed == 100) || (speed == 1000) )
  1115. out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
  1116. else
  1117. out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
  1118. if ((devnum == 2) || (devnum == 3)) {
  1119. if (speed == 1000)
  1120. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
  1121. else if (speed == 100)
  1122. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
  1123. else if (speed == 10)
  1124. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
  1125. else {
  1126. printf("Error in RGMII Speed\n");
  1127. return -1;
  1128. }
  1129. out_be32((void *)RGMII_SSR, reg);
  1130. }
  1131. #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
  1132. #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1133. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1134. defined(CONFIG_405EX)
  1135. if (devnum >= 2)
  1136. rgmii_channel = devnum - 2;
  1137. else
  1138. rgmii_channel = devnum;
  1139. if (speed == 1000)
  1140. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
  1141. else if (speed == 100)
  1142. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
  1143. else if (speed == 10)
  1144. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
  1145. else {
  1146. printf("Error in RGMII Speed\n");
  1147. return -1;
  1148. }
  1149. out_be32((void *)RGMII_SSR, reg);
  1150. #if defined(CONFIG_460GT)
  1151. if ((devnum == 2) || (devnum == 3))
  1152. out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
  1153. #endif
  1154. #endif
  1155. /* set the Mal configuration reg */
  1156. #if defined(CONFIG_440GX) || \
  1157. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1158. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  1159. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1160. defined(CONFIG_405EX)
  1161. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
  1162. MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  1163. #else
  1164. mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
  1165. /* Errata 1.12: MAL_1 -- Disable MAL bursting */
  1166. if (get_pvr() == PVR_440GP_RB) {
  1167. mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
  1168. }
  1169. #endif
  1170. /*
  1171. * Malloc MAL buffer desciptors, make sure they are
  1172. * aligned on cache line boundary size
  1173. * (401/403/IOP480 = 16, 405 = 32)
  1174. * and doesn't cross cache block boundaries.
  1175. */
  1176. if (hw_p->first_init == 0) {
  1177. debug("*** Allocating descriptor memory ***\n");
  1178. bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
  1179. if (!bd_cached) {
  1180. printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
  1181. return -1;
  1182. }
  1183. #ifdef CONFIG_4xx_DCACHE
  1184. flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
  1185. if (!last_used_ea)
  1186. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  1187. bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
  1188. #else
  1189. bd_uncached = bis->bi_memsize;
  1190. #endif
  1191. else
  1192. bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
  1193. last_used_ea = bd_uncached;
  1194. program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
  1195. TLB_WORD2_I_ENABLE);
  1196. #else
  1197. bd_uncached = bd_cached;
  1198. #endif
  1199. hw_p->tx_phys = bd_cached;
  1200. hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
  1201. hw_p->tx = (mal_desc_t *)(bd_uncached);
  1202. hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
  1203. debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
  1204. }
  1205. for (i = 0; i < NUM_TX_BUFF; i++) {
  1206. hw_p->tx[i].ctrl = 0;
  1207. hw_p->tx[i].data_len = 0;
  1208. if (hw_p->first_init == 0)
  1209. hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
  1210. L1_CACHE_BYTES);
  1211. hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
  1212. if ((NUM_TX_BUFF - 1) == i)
  1213. hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
  1214. hw_p->tx_run[i] = -1;
  1215. debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
  1216. }
  1217. for (i = 0; i < NUM_RX_BUFF; i++) {
  1218. hw_p->rx[i].ctrl = 0;
  1219. hw_p->rx[i].data_len = 0;
  1220. hw_p->rx[i].data_ptr = (char *)net_rx_packets[i];
  1221. if ((NUM_RX_BUFF - 1) == i)
  1222. hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
  1223. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
  1224. hw_p->rx_ready[i] = -1;
  1225. debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
  1226. }
  1227. reg = 0x00000000;
  1228. reg |= dev->enetaddr[0]; /* set high address */
  1229. reg = reg << 8;
  1230. reg |= dev->enetaddr[1];
  1231. out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
  1232. reg = 0x00000000;
  1233. reg |= dev->enetaddr[2]; /* set low address */
  1234. reg = reg << 8;
  1235. reg |= dev->enetaddr[3];
  1236. reg = reg << 8;
  1237. reg |= dev->enetaddr[4];
  1238. reg = reg << 8;
  1239. reg |= dev->enetaddr[5];
  1240. out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
  1241. switch (devnum) {
  1242. case 1:
  1243. /* setup MAL tx & rx channel pointers */
  1244. #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
  1245. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1246. #else
  1247. mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
  1248. #endif
  1249. #if defined(CONFIG_440)
  1250. mtdcr (MAL0_TXBADDR, 0x0);
  1251. mtdcr (MAL0_RXBADDR, 0x0);
  1252. #endif
  1253. #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  1254. mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
  1255. /* set RX buffer size */
  1256. mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
  1257. #else
  1258. mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
  1259. /* set RX buffer size */
  1260. mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
  1261. #endif
  1262. break;
  1263. #if defined (CONFIG_440GX)
  1264. case 2:
  1265. /* setup MAL tx & rx channel pointers */
  1266. mtdcr (MAL0_TXBADDR, 0x0);
  1267. mtdcr (MAL0_RXBADDR, 0x0);
  1268. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1269. mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
  1270. /* set RX buffer size */
  1271. mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
  1272. break;
  1273. case 3:
  1274. /* setup MAL tx & rx channel pointers */
  1275. mtdcr (MAL0_TXBADDR, 0x0);
  1276. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1277. mtdcr (MAL0_RXBADDR, 0x0);
  1278. mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
  1279. /* set RX buffer size */
  1280. mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
  1281. break;
  1282. #endif /* CONFIG_440GX */
  1283. #if defined (CONFIG_460GT)
  1284. case 2:
  1285. /* setup MAL tx & rx channel pointers */
  1286. mtdcr (MAL0_TXBADDR, 0x0);
  1287. mtdcr (MAL0_RXBADDR, 0x0);
  1288. mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
  1289. mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
  1290. /* set RX buffer size */
  1291. mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
  1292. break;
  1293. case 3:
  1294. /* setup MAL tx & rx channel pointers */
  1295. mtdcr (MAL0_TXBADDR, 0x0);
  1296. mtdcr (MAL0_RXBADDR, 0x0);
  1297. mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
  1298. mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
  1299. /* set RX buffer size */
  1300. mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
  1301. break;
  1302. #endif /* CONFIG_460GT */
  1303. case 0:
  1304. default:
  1305. /* setup MAL tx & rx channel pointers */
  1306. #if defined(CONFIG_440)
  1307. mtdcr (MAL0_TXBADDR, 0x0);
  1308. mtdcr (MAL0_RXBADDR, 0x0);
  1309. #endif
  1310. mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
  1311. mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
  1312. /* set RX buffer size */
  1313. mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
  1314. break;
  1315. }
  1316. /* Enable MAL transmit and receive channels */
  1317. #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
  1318. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
  1319. #else
  1320. mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1321. #endif
  1322. mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
  1323. /* set transmit enable & receive enable */
  1324. out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
  1325. mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
  1326. /* set rx-/tx-fifo size */
  1327. mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
  1328. /* set speed */
  1329. if (speed == _1000BASET) {
  1330. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  1331. unsigned long pfc1;
  1332. mfsdr (SDR0_PFC1, pfc1);
  1333. pfc1 |= SDR0_PFC1_EM_1000;
  1334. mtsdr (SDR0_PFC1, pfc1);
  1335. #endif
  1336. mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
  1337. } else if (speed == _100BASET)
  1338. mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
  1339. else
  1340. mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
  1341. if (duplex == FULL)
  1342. mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
  1343. out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
  1344. /* Enable broadcast and indvidual address */
  1345. /* TBS: enabling runts as some misbehaved nics will send runts */
  1346. out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
  1347. /* we probably need to set the tx mode1 reg? maybe at tx time */
  1348. /* set transmit request threshold register */
  1349. out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
  1350. /* set receive low/high water mark register */
  1351. #if defined(CONFIG_440)
  1352. /* 440s has a 64 byte burst length */
  1353. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
  1354. #else
  1355. /* 405s have a 16 byte burst length */
  1356. out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
  1357. #endif /* defined(CONFIG_440) */
  1358. out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
  1359. /* Set fifo limit entry in tx mode 0 */
  1360. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
  1361. /* Frame gap set */
  1362. out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
  1363. /* Set EMAC IER */
  1364. hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
  1365. if (speed == _100BASET)
  1366. hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
  1367. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
  1368. out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
  1369. if (hw_p->first_init == 0) {
  1370. /*
  1371. * Connect interrupt service routines
  1372. */
  1373. irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
  1374. (interrupt_handler_t *) enetInt, dev);
  1375. }
  1376. mtmsr (msr); /* enable interrupts again */
  1377. hw_p->bis = bis;
  1378. hw_p->first_init = 1;
  1379. return 0;
  1380. }
  1381. static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
  1382. {
  1383. struct enet_frame *ef_ptr;
  1384. ulong time_start, time_now;
  1385. unsigned long temp_txm0;
  1386. EMAC_4XX_HW_PST hw_p = dev->priv;
  1387. ef_ptr = (struct enet_frame *) ptr;
  1388. /*-----------------------------------------------------------------------+
  1389. * Copy in our address into the frame.
  1390. *-----------------------------------------------------------------------*/
  1391. (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
  1392. /*-----------------------------------------------------------------------+
  1393. * If frame is too long or too short, modify length.
  1394. *-----------------------------------------------------------------------*/
  1395. /* TBS: where does the fragment go???? */
  1396. if (len > ENET_MAX_MTU)
  1397. len = ENET_MAX_MTU;
  1398. /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
  1399. memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
  1400. flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
  1401. /*-----------------------------------------------------------------------+
  1402. * set TX Buffer busy, and send it
  1403. *-----------------------------------------------------------------------*/
  1404. hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
  1405. EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
  1406. ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
  1407. if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
  1408. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
  1409. hw_p->tx[hw_p->tx_slot].data_len = (short) len;
  1410. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
  1411. sync();
  1412. out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
  1413. in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
  1414. #ifdef INFO_4XX_ENET
  1415. hw_p->stats.pkts_tx++;
  1416. #endif
  1417. /*-----------------------------------------------------------------------+
  1418. * poll unitl the packet is sent and then make sure it is OK
  1419. *-----------------------------------------------------------------------*/
  1420. time_start = get_timer (0);
  1421. while (1) {
  1422. temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
  1423. /* loop until either TINT turns on or 3 seconds elapse */
  1424. if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
  1425. /* transmit is done, so now check for errors
  1426. * If there is an error, an interrupt should
  1427. * happen when we return
  1428. */
  1429. time_now = get_timer (0);
  1430. if ((time_now - time_start) > 3000) {
  1431. return (-1);
  1432. }
  1433. } else {
  1434. return (len);
  1435. }
  1436. }
  1437. }
  1438. int enetInt (struct eth_device *dev)
  1439. {
  1440. int serviced;
  1441. int rc = -1; /* default to not us */
  1442. u32 mal_isr;
  1443. u32 emac_isr = 0;
  1444. u32 mal_eob;
  1445. u32 uic_mal;
  1446. u32 uic_mal_err;
  1447. u32 uic_emac;
  1448. u32 uic_emac_b;
  1449. EMAC_4XX_HW_PST hw_p;
  1450. /*
  1451. * Because the mal is generic, we need to get the current
  1452. * eth device
  1453. */
  1454. dev = eth_get_dev();
  1455. hw_p = dev->priv;
  1456. /* enter loop that stays in interrupt code until nothing to service */
  1457. do {
  1458. serviced = 0;
  1459. uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
  1460. uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
  1461. uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
  1462. uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
  1463. if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
  1464. && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
  1465. && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
  1466. /* not for us */
  1467. return (rc);
  1468. }
  1469. /* get and clear controller status interrupts */
  1470. /* look at MAL and EMAC error interrupts */
  1471. if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
  1472. /* we have a MAL error interrupt */
  1473. mal_isr = mfdcr(MAL0_ESR);
  1474. mal_err(dev, mal_isr, uic_mal_err,
  1475. MAL_UIC_DEF, MAL_UIC_ERR);
  1476. /* clear MAL error interrupt status bits */
  1477. mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
  1478. UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
  1479. return -1;
  1480. }
  1481. /* look for EMAC errors */
  1482. if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
  1483. emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
  1484. emac_err(dev, emac_isr);
  1485. /* clear EMAC error interrupt status bits */
  1486. mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
  1487. mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
  1488. return -1;
  1489. }
  1490. /* handle MAX TX EOB interrupt from a tx */
  1491. if (uic_mal & UIC_MAL_TXEOB) {
  1492. /* clear MAL interrupt status bits */
  1493. mal_eob = mfdcr(MAL0_TXEOBISR);
  1494. mtdcr(MAL0_TXEOBISR, mal_eob);
  1495. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
  1496. /* indicate that we serviced an interrupt */
  1497. serviced = 1;
  1498. rc = 0;
  1499. }
  1500. /* handle MAL RX EOB interrupt from a receive */
  1501. /* check for EOB on valid channels */
  1502. if (uic_mal & UIC_MAL_RXEOB) {
  1503. mal_eob = mfdcr(MAL0_RXEOBISR);
  1504. if (mal_eob &
  1505. (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
  1506. /* push packet to upper layer */
  1507. enet_rcv(dev, emac_isr);
  1508. /* clear MAL interrupt status bits */
  1509. mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
  1510. /* indicate that we serviced an interrupt */
  1511. serviced = 1;
  1512. rc = 0;
  1513. }
  1514. }
  1515. #if defined(CONFIG_405EZ)
  1516. /*
  1517. * On 405EZ the RX-/TX-interrupts are coalesced into
  1518. * one IRQ bit in the UIC. We need to acknowledge the
  1519. * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
  1520. */
  1521. mtsdr(SDR0_ICINTSTAT,
  1522. SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
  1523. #endif /* defined(CONFIG_405EZ) */
  1524. } while (serviced);
  1525. return (rc);
  1526. }
  1527. /*-----------------------------------------------------------------------------+
  1528. * MAL Error Routine
  1529. *-----------------------------------------------------------------------------*/
  1530. static void mal_err (struct eth_device *dev, unsigned long isr,
  1531. unsigned long uic, unsigned long maldef,
  1532. unsigned long mal_errr)
  1533. {
  1534. mtdcr (MAL0_ESR, isr); /* clear interrupt */
  1535. /* clear DE interrupt */
  1536. mtdcr (MAL0_TXDEIR, 0xC0000000);
  1537. mtdcr (MAL0_RXDEIR, 0x80000000);
  1538. #ifdef INFO_4XX_ENET
  1539. printf("\nMAL error occurred.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx\n",
  1540. isr, uic, maldef, mal_errr);
  1541. #endif
  1542. eth_init(); /* start again... */
  1543. }
  1544. /*-----------------------------------------------------------------------------+
  1545. * EMAC Error Routine
  1546. *-----------------------------------------------------------------------------*/
  1547. static void emac_err (struct eth_device *dev, unsigned long isr)
  1548. {
  1549. EMAC_4XX_HW_PST hw_p = dev->priv;
  1550. printf ("EMAC%d error occurred.... ISR = %lx\n", hw_p->devnum, isr);
  1551. out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
  1552. }
  1553. /*-----------------------------------------------------------------------------+
  1554. * enet_rcv() handles the ethernet receive data
  1555. *-----------------------------------------------------------------------------*/
  1556. static void enet_rcv (struct eth_device *dev, unsigned long malisr)
  1557. {
  1558. unsigned long data_len;
  1559. unsigned long rx_eob_isr;
  1560. EMAC_4XX_HW_PST hw_p = dev->priv;
  1561. int handled = 0;
  1562. int i;
  1563. int loop_count = 0;
  1564. rx_eob_isr = mfdcr (MAL0_RXEOBISR);
  1565. if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
  1566. /* clear EOB */
  1567. mtdcr (MAL0_RXEOBISR, rx_eob_isr);
  1568. /* EMAC RX done */
  1569. while (1) { /* do all */
  1570. i = hw_p->rx_slot;
  1571. if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
  1572. || (loop_count >= NUM_RX_BUFF))
  1573. break;
  1574. loop_count++;
  1575. handled++;
  1576. data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
  1577. if (data_len) {
  1578. if (data_len > ENET_MAX_MTU) /* Check len */
  1579. data_len = 0;
  1580. else {
  1581. if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
  1582. data_len = 0;
  1583. hw_p->stats.rx_err_log[hw_p->
  1584. rx_err_index]
  1585. = hw_p->rx[i].ctrl;
  1586. hw_p->rx_err_index++;
  1587. if (hw_p->rx_err_index ==
  1588. MAX_ERR_LOG)
  1589. hw_p->rx_err_index =
  1590. 0;
  1591. } /* emac_erros */
  1592. } /* data_len < max mtu */
  1593. } /* if data_len */
  1594. if (!data_len) { /* no data */
  1595. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
  1596. hw_p->stats.data_len_err++; /* Error at Rx */
  1597. }
  1598. /* !data_len */
  1599. /* AS.HARNOIS */
  1600. /* Check if user has already eaten buffer */
  1601. /* if not => ERROR */
  1602. else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
  1603. if (hw_p->is_receiving)
  1604. printf ("ERROR : Receive buffers are full!\n");
  1605. break;
  1606. } else {
  1607. hw_p->stats.rx_frames++;
  1608. hw_p->stats.rx += data_len;
  1609. #ifdef INFO_4XX_ENET
  1610. hw_p->stats.pkts_rx++;
  1611. #endif
  1612. /* AS.HARNOIS
  1613. * use ring buffer
  1614. */
  1615. hw_p->rx_ready[hw_p->rx_i_index] = i;
  1616. hw_p->rx_i_index++;
  1617. if (NUM_RX_BUFF == hw_p->rx_i_index)
  1618. hw_p->rx_i_index = 0;
  1619. hw_p->rx_slot++;
  1620. if (NUM_RX_BUFF == hw_p->rx_slot)
  1621. hw_p->rx_slot = 0;
  1622. /* AS.HARNOIS
  1623. * free receive buffer only when
  1624. * buffer has been handled (eth_rx)
  1625. rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
  1626. */
  1627. } /* if data_len */
  1628. } /* while */
  1629. } /* if EMACK_RXCHL */
  1630. }
  1631. static int ppc_4xx_eth_rx (struct eth_device *dev)
  1632. {
  1633. int length;
  1634. int user_index;
  1635. unsigned long msr;
  1636. EMAC_4XX_HW_PST hw_p = dev->priv;
  1637. hw_p->is_receiving = 1; /* tell driver */
  1638. for (;;) {
  1639. /* AS.HARNOIS
  1640. * use ring buffer and
  1641. * get index from rx buffer desciptor queue
  1642. */
  1643. user_index = hw_p->rx_ready[hw_p->rx_u_index];
  1644. if (user_index == -1) {
  1645. length = -1;
  1646. break; /* nothing received - leave for() loop */
  1647. }
  1648. msr = mfmsr ();
  1649. mtmsr (msr & ~(MSR_EE));
  1650. length = hw_p->rx[user_index].data_len & 0x0fff;
  1651. /*
  1652. * Pass the packet up to the protocol layers.
  1653. * net_process_received_packet(net_rx_packets[rxIdx],
  1654. * length - 4);
  1655. * net_process_received_packet(net_rx_packets[i], length);
  1656. */
  1657. invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
  1658. (u32)hw_p->rx[user_index].data_ptr +
  1659. length - 4);
  1660. net_process_received_packet(net_rx_packets[user_index],
  1661. length - 4);
  1662. /* Free Recv Buffer */
  1663. hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
  1664. /* Free rx buffer descriptor queue */
  1665. hw_p->rx_ready[hw_p->rx_u_index] = -1;
  1666. hw_p->rx_u_index++;
  1667. if (NUM_RX_BUFF == hw_p->rx_u_index)
  1668. hw_p->rx_u_index = 0;
  1669. #ifdef INFO_4XX_ENET
  1670. hw_p->stats.pkts_handled++;
  1671. #endif
  1672. mtmsr (msr); /* Enable IRQ's */
  1673. }
  1674. hw_p->is_receiving = 0; /* tell driver */
  1675. return length;
  1676. }
  1677. int ppc_4xx_eth_initialize (bd_t * bis)
  1678. {
  1679. static int virgin = 0;
  1680. struct eth_device *dev;
  1681. int eth_num = 0;
  1682. EMAC_4XX_HW_PST hw = NULL;
  1683. u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
  1684. u32 hw_addr[4];
  1685. u32 mal_ier;
  1686. #if defined(CONFIG_440GX)
  1687. unsigned long pfc1;
  1688. mfsdr (SDR0_PFC1, pfc1);
  1689. pfc1 &= ~(0x01e00000);
  1690. pfc1 |= 0x01200000;
  1691. mtsdr (SDR0_PFC1, pfc1);
  1692. #endif
  1693. /* first clear all mac-addresses */
  1694. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
  1695. memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
  1696. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1697. int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
  1698. switch (eth_num) {
  1699. default: /* fall through */
  1700. case 0:
  1701. eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
  1702. hw_addr[eth_num] = 0x0;
  1703. break;
  1704. #ifdef CONFIG_HAS_ETH1
  1705. case 1:
  1706. eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
  1707. hw_addr[eth_num] = 0x100;
  1708. break;
  1709. #endif
  1710. #ifdef CONFIG_HAS_ETH2
  1711. case 2:
  1712. eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
  1713. #if defined(CONFIG_460GT)
  1714. hw_addr[eth_num] = 0x300;
  1715. #else
  1716. hw_addr[eth_num] = 0x400;
  1717. #endif
  1718. break;
  1719. #endif
  1720. #ifdef CONFIG_HAS_ETH3
  1721. case 3:
  1722. eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
  1723. #if defined(CONFIG_460GT)
  1724. hw_addr[eth_num] = 0x400;
  1725. #else
  1726. hw_addr[eth_num] = 0x600;
  1727. #endif
  1728. break;
  1729. #endif
  1730. }
  1731. }
  1732. /* set phy num and mode */
  1733. bis->bi_phynum[0] = CONFIG_PHY_ADDR;
  1734. bis->bi_phymode[0] = 0;
  1735. #if defined(CONFIG_PHY1_ADDR)
  1736. bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
  1737. bis->bi_phymode[1] = 0;
  1738. #endif
  1739. #if defined(CONFIG_440GX)
  1740. bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
  1741. bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
  1742. bis->bi_phymode[2] = 2;
  1743. bis->bi_phymode[3] = 2;
  1744. #endif
  1745. #if defined(CONFIG_440GX) || \
  1746. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1747. defined(CONFIG_405EX)
  1748. ppc_4xx_eth_setup_bridge(0, bis);
  1749. #endif
  1750. for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
  1751. /*
  1752. * See if we can actually bring up the interface,
  1753. * otherwise, skip it
  1754. */
  1755. if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
  1756. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1757. continue;
  1758. }
  1759. /* Allocate device structure */
  1760. dev = (struct eth_device *) malloc (sizeof (*dev));
  1761. if (dev == NULL) {
  1762. printf ("ppc_4xx_eth_initialize: "
  1763. "Cannot allocate eth_device %d\n", eth_num);
  1764. return (-1);
  1765. }
  1766. memset(dev, 0, sizeof(*dev));
  1767. /* Allocate our private use data */
  1768. hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
  1769. if (hw == NULL) {
  1770. printf ("ppc_4xx_eth_initialize: "
  1771. "Cannot allocate private hw data for eth_device %d",
  1772. eth_num);
  1773. free (dev);
  1774. return (-1);
  1775. }
  1776. memset(hw, 0, sizeof(*hw));
  1777. hw->hw_addr = hw_addr[eth_num];
  1778. memcpy (dev->enetaddr, ethaddr[eth_num], 6);
  1779. hw->devnum = eth_num;
  1780. hw->print_speed = 1;
  1781. sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
  1782. dev->priv = (void *) hw;
  1783. dev->init = ppc_4xx_eth_init;
  1784. dev->halt = ppc_4xx_eth_halt;
  1785. dev->send = ppc_4xx_eth_send;
  1786. dev->recv = ppc_4xx_eth_rx;
  1787. eth_register(dev);
  1788. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  1789. int retval;
  1790. struct mii_dev *mdiodev = mdio_alloc();
  1791. if (!mdiodev)
  1792. return -ENOMEM;
  1793. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  1794. mdiodev->read = emac4xx_miiphy_read;
  1795. mdiodev->write = emac4xx_miiphy_write;
  1796. retval = mdio_register(mdiodev);
  1797. if (retval < 0)
  1798. return retval;
  1799. #endif
  1800. if (0 == virgin) {
  1801. /* set the MAL IER ??? names may change with new spec ??? */
  1802. #if defined(CONFIG_440SPE) || \
  1803. defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  1804. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1805. defined(CONFIG_405EX)
  1806. mal_ier =
  1807. MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
  1808. MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
  1809. #else
  1810. mal_ier =
  1811. MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
  1812. MAL_IER_OPBE | MAL_IER_PLBE;
  1813. #endif
  1814. mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
  1815. mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
  1816. mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
  1817. mtdcr (MAL0_IER, mal_ier);
  1818. /* install MAL interrupt handler */
  1819. irq_install_handler (VECNUM_MAL_SERR,
  1820. (interrupt_handler_t *) enetInt,
  1821. dev);
  1822. irq_install_handler (VECNUM_MAL_TXEOB,
  1823. (interrupt_handler_t *) enetInt,
  1824. dev);
  1825. irq_install_handler (VECNUM_MAL_RXEOB,
  1826. (interrupt_handler_t *) enetInt,
  1827. dev);
  1828. irq_install_handler (VECNUM_MAL_TXDE,
  1829. (interrupt_handler_t *) enetInt,
  1830. dev);
  1831. irq_install_handler (VECNUM_MAL_RXDE,
  1832. (interrupt_handler_t *) enetInt,
  1833. dev);
  1834. virgin = 1;
  1835. }
  1836. } /* end for each supported device */
  1837. return 0;
  1838. }