processor.h 56 KB

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  1. #ifndef __ASM_PPC_PROCESSOR_H
  2. #define __ASM_PPC_PROCESSOR_H
  3. /*
  4. * Default implementation of macro that returns current
  5. * instruction pointer ("program counter").
  6. */
  7. #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  8. #include <asm/ptrace.h>
  9. #include <asm/types.h>
  10. /* Machine State Register (MSR) Fields */
  11. #ifdef CONFIG_PPC64BRIDGE
  12. #define MSR_SF (1<<63)
  13. #define MSR_ISF (1<<61)
  14. #endif /* CONFIG_PPC64BRIDGE */
  15. #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
  16. #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
  17. #define MSR_SPE (1<<25) /* Enable SPE(e500) */
  18. #define MSR_POW (1<<18) /* Enable Power Management */
  19. #define MSR_WE (1<<18) /* Wait State Enable */
  20. #define MSR_TGPR (1<<17) /* TLB Update registers in use */
  21. #define MSR_CE (1<<17) /* Critical Interrupt Enable */
  22. #define MSR_ILE (1<<16) /* Interrupt Little Endian */
  23. #define MSR_EE (1<<15) /* External Interrupt Enable */
  24. #define MSR_PR (1<<14) /* Problem State / Privilege Level */
  25. #define MSR_FP (1<<13) /* Floating Point enable */
  26. #define MSR_ME (1<<12) /* Machine Check Enable */
  27. #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
  28. #define MSR_SE (1<<10) /* Single Step */
  29. #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
  30. #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
  31. #define MSR_BE (1<<9) /* Branch Trace */
  32. #define MSR_DE (1<<9) /* Debug Exception Enable */
  33. #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
  34. #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
  35. #define MSR_IR (1<<5) /* Instruction Relocate */
  36. #define MSR_IS (1<<5) /* Book E Instruction space */
  37. #define MSR_DR (1<<4) /* Data Relocate */
  38. #define MSR_DS (1<<4) /* Book E Data space */
  39. #define MSR_PE (1<<3) /* Protection Enable */
  40. #define MSR_PX (1<<2) /* Protection Exclusive Mode */
  41. #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
  42. #define MSR_RI (1<<1) /* Recoverable Exception */
  43. #define MSR_LE (1<<0) /* Little Endian */
  44. #ifdef CONFIG_APUS_FAST_EXCEPT
  45. #define MSR_ MSR_ME|MSR_IP|MSR_RI
  46. #else
  47. #define MSR_ MSR_ME|MSR_RI
  48. #endif
  49. #ifndef CONFIG_E500
  50. #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
  51. #else
  52. #define MSR_KERNEL MSR_ME
  53. #endif
  54. /* Floating Point Status and Control Register (FPSCR) Fields */
  55. #define FPSCR_FX 0x80000000 /* FPU exception summary */
  56. #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
  57. #define FPSCR_VX 0x20000000 /* Invalid operation summary */
  58. #define FPSCR_OX 0x10000000 /* Overflow exception summary */
  59. #define FPSCR_UX 0x08000000 /* Underflow exception summary */
  60. #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
  61. #define FPSCR_XX 0x02000000 /* Inexact exception summary */
  62. #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
  63. #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
  64. #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
  65. #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
  66. #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
  67. #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
  68. #define FPSCR_FR 0x00040000 /* Fraction rounded */
  69. #define FPSCR_FI 0x00020000 /* Fraction inexact */
  70. #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
  71. #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
  72. #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
  73. #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
  74. #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
  75. #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
  76. #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
  77. #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
  78. #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
  79. #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
  80. #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
  81. #define FPSCR_RN 0x00000003 /* FPU rounding control */
  82. /* Special Purpose Registers (SPRNs)*/
  83. /* PPC440 Architecture is BOOK-E */
  84. #ifdef CONFIG_440
  85. #define CONFIG_BOOKE
  86. #endif
  87. #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
  88. #ifdef CONFIG_BOOKE
  89. #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
  90. #endif
  91. #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
  92. #define SPRN_CTR 0x009 /* Count Register */
  93. #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
  94. #ifndef CONFIG_BOOKE
  95. #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
  96. #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
  97. #else
  98. #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
  99. #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
  100. #endif /* CONFIG_BOOKE */
  101. #define SPRN_DAR 0x013 /* Data Address Register */
  102. #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
  103. #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
  104. #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
  105. #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
  106. #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
  107. #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
  108. #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
  109. #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
  110. #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
  111. #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
  112. #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
  113. #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
  114. #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
  115. #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
  116. #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
  117. #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
  118. #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
  119. #define DBCR_EDM 0x80000000
  120. #define DBCR_IDM 0x40000000
  121. #define DBCR_RST(x) (((x) & 0x3) << 28)
  122. #define DBCR_RST_NONE 0
  123. #define DBCR_RST_CORE 1
  124. #define DBCR_RST_CHIP 2
  125. #define DBCR_RST_SYSTEM 3
  126. #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
  127. #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
  128. #define DBCR_EDE 0x02000000 /* Exception Debug Event */
  129. #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
  130. #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
  131. #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
  132. #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
  133. #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
  134. #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
  135. #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
  136. #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
  137. #define DAC_BYTE 0
  138. #define DAC_HALF 1
  139. #define DAC_WORD 2
  140. #define DAC_QUAD 3
  141. #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
  142. #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
  143. #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
  144. #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
  145. #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
  146. #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
  147. #define DBCR_SIA 0x00000008 /* Second IAC Enable */
  148. #define DBCR_SDA 0x00000004 /* Second DAC Enable */
  149. #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
  150. #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
  151. #ifndef CONFIG_BOOKE
  152. #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
  153. #else
  154. #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
  155. #endif /* CONFIG_BOOKE */
  156. #ifndef CONFIG_BOOKE
  157. #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
  158. #define SPRN_DBSR 0x3F0 /* Debug Status Register */
  159. #else
  160. #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
  161. #ifdef CONFIG_BOOKE
  162. #define SPRN_DBDR 0x3f3 /* Debug Data Register */
  163. #endif
  164. #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
  165. #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
  166. #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
  167. #endif /* CONFIG_BOOKE */
  168. #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
  169. #define DCCR_NOCACHE 0 /* Noncacheable */
  170. #define DCCR_CACHE 1 /* Cacheable */
  171. #ifndef CONFIG_BOOKE
  172. #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
  173. #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
  174. #endif
  175. #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
  176. #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
  177. #define DCWR_COPY 0 /* Copy-back */
  178. #define DCWR_WRITE 1 /* Write-through */
  179. #ifndef CONFIG_BOOKE
  180. #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
  181. #else
  182. #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
  183. #endif /* CONFIG_BOOKE */
  184. #define SPRN_DEC 0x016 /* Decrement Register */
  185. #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
  186. #ifdef CONFIG_BOOKE
  187. #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
  188. #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
  189. #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
  190. #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
  191. #endif
  192. #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
  193. #ifdef CONFIG_BOOKE
  194. #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
  195. #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
  196. #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
  197. #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
  198. #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
  199. #endif
  200. #define SPRN_EAR 0x11A /* External Address Register */
  201. #ifndef CONFIG_BOOKE
  202. #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
  203. #else
  204. #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
  205. #endif /* CONFIG_BOOKE */
  206. #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
  207. #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
  208. #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
  209. #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
  210. #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
  211. #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
  212. #define ESR_PTR 0x02000000 /* Program Exception - Trap */
  213. #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
  214. #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
  215. #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
  216. #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
  217. #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
  218. #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
  219. #define HID0_ICE_SHIFT 15
  220. #define HID0_DCE_SHIFT 14
  221. #define HID0_DLOCK_SHIFT 12
  222. #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
  223. #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
  224. #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
  225. #define HID0_SBCLK (1<<27)
  226. #define HID0_EICE (1<<26)
  227. #define HID0_ECLK (1<<25)
  228. #define HID0_PAR (1<<24)
  229. #define HID0_DOZE (1<<23)
  230. #define HID0_NAP (1<<22)
  231. #define HID0_SLEEP (1<<21)
  232. #define HID0_DPM (1<<20)
  233. #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
  234. #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
  235. #define HID0_TBEN (1<<14) /* Time Base Enable */
  236. #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
  237. #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
  238. #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
  239. #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
  240. #define HID0_DCI HID0_DCFI
  241. #define HID0_SPD (1<<9) /* Speculative disable */
  242. #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
  243. #define HID0_SGE (1<<7) /* Store Gathering Enable */
  244. #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
  245. #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
  246. #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
  247. #define HID0_ABE (1<<3) /* Address Broadcast Enable */
  248. #define HID0_BHTE (1<<2) /* Branch History Table Enable */
  249. #define HID0_BTCD (1<<1) /* Branch target cache disable */
  250. #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
  251. #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
  252. #define HID1_ASTME (1<<13) /* Address bus streaming mode */
  253. #define HID1_ABE (1<<12) /* Address broadcast enable */
  254. #define HID1_MBDD (1<<6) /* optimized sync instruction */
  255. #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
  256. #ifndef CONFIG_BOOKE
  257. #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
  258. #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
  259. #else
  260. #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
  261. #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
  262. #endif /* CONFIG_BOOKE */
  263. #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
  264. #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
  265. #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
  266. #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
  267. #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
  268. #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
  269. #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
  270. #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
  271. #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
  272. #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
  273. #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
  274. #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
  275. #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
  276. #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
  277. #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
  278. #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
  279. #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
  280. #define ICCR_NOCACHE 0 /* Noncacheable */
  281. #define ICCR_CACHE 1 /* Cacheable */
  282. #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
  283. #ifdef CONFIG_BOOKE
  284. #define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
  285. #define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
  286. #endif
  287. #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
  288. #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
  289. #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
  290. #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
  291. #ifdef CONFIG_BOOKE
  292. #define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
  293. #define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
  294. #define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
  295. #define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
  296. #define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
  297. #define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
  298. #define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
  299. #define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
  300. #define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
  301. #endif
  302. #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
  303. #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
  304. #define SPRN_LR 0x008 /* Link Register */
  305. #define SPRN_MBAR 0x137 /* System memory base address */
  306. #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
  307. #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
  308. #ifdef CONFIG_BOOKE
  309. #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
  310. #endif
  311. #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
  312. #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
  313. #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
  314. #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
  315. #ifndef CONFIG_BOOKE
  316. #define SPRN_PID 0x3B1 /* Process ID */
  317. #define SPRN_PIR 0x3FF /* Processor Identification Register */
  318. #else
  319. #define SPRN_PID 0x030 /* Book E Process ID */
  320. #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
  321. #endif /* CONFIG_BOOKE */
  322. #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
  323. #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
  324. #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
  325. #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
  326. #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
  327. #define SPRN_PVR 0x11F /* Processor Version Register */
  328. #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
  329. #ifdef CONFIG_BOOKE
  330. #define SPRN_RSTCFG 0x39b /* Reset Configuration */
  331. #endif
  332. #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
  333. #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
  334. #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
  335. #define SGR_NORMAL 0
  336. #define SGR_GUARDED 1
  337. #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
  338. #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
  339. #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
  340. #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
  341. #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
  342. #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
  343. #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
  344. #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
  345. #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
  346. #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
  347. #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
  348. #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
  349. #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
  350. #ifdef CONFIG_BOOKE
  351. #define SPRN_SVR 0x3FF /* System Version Register */
  352. #else
  353. #define SPRN_SVR 0x11E /* System Version Register */
  354. #endif
  355. #define SPRN_TBHI 0x3DC /* Time Base High */
  356. #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
  357. #define SPRN_TBLO 0x3DD /* Time Base Low */
  358. #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
  359. #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
  360. #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
  361. #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
  362. #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
  363. #ifndef CONFIG_BOOKE
  364. #define SPRN_TCR 0x3DA /* Timer Control Register */
  365. #else
  366. #define SPRN_TCR 0x154 /* Book E Timer Control Register */
  367. #endif /* CONFIG_BOOKE */
  368. #ifdef CONFIG_E500MC
  369. #define TCR_WP(x) (((64-x)&0x3)<<30)| \
  370. (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
  371. #else
  372. #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
  373. #define WP_2_17 0 /* 2^17 clocks */
  374. #define WP_2_21 1 /* 2^21 clocks */
  375. #define WP_2_25 2 /* 2^25 clocks */
  376. #define WP_2_29 3 /* 2^29 clocks */
  377. #endif /* CONFIG_E500 */
  378. #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
  379. #define WRC_NONE 0 /* No reset will occur */
  380. #define WRC_CORE 1 /* Core reset will occur */
  381. #define WRC_CHIP 2 /* Chip reset will occur */
  382. #define WRC_SYSTEM 3 /* System reset will occur */
  383. #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
  384. #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
  385. #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
  386. #define FP_2_9 0 /* 2^9 clocks */
  387. #define FP_2_13 1 /* 2^13 clocks */
  388. #define FP_2_17 2 /* 2^17 clocks */
  389. #define FP_2_21 3 /* 2^21 clocks */
  390. #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
  391. #define TCR_ARE 0x00400000 /* Auto Reload Enable */
  392. #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
  393. #define THRM1_TIN (1<<0)
  394. #define THRM1_TIV (1<<1)
  395. #define THRM1_THRES (0x7f<<2)
  396. #define THRM1_TID (1<<29)
  397. #define THRM1_TIE (1<<30)
  398. #define THRM1_V (1<<31)
  399. #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
  400. #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
  401. #define THRM3_E (1<<31)
  402. #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
  403. #ifndef CONFIG_BOOKE
  404. #define SPRN_TSR 0x3D8 /* Timer Status Register */
  405. #else
  406. #define SPRN_TSR 0x150 /* Book E Timer Status Register */
  407. #endif /* CONFIG_BOOKE */
  408. #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
  409. #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
  410. #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
  411. #define WRS_NONE 0 /* No WDT reset occurred */
  412. #define WRS_CORE 1 /* WDT forced core reset */
  413. #define WRS_CHIP 2 /* WDT forced chip reset */
  414. #define WRS_SYSTEM 3 /* WDT forced system reset */
  415. #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
  416. #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
  417. #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
  418. #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
  419. #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
  420. #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
  421. #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
  422. #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
  423. #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
  424. #define SPRN_XER 0x001 /* Fixed Point Exception Register */
  425. #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
  426. /* Book E definitions */
  427. #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
  428. #define SPRN_CSRR0 0x03A /* Critical SRR0 */
  429. #define SPRN_CSRR1 0x03B /* Critical SRR0 */
  430. #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
  431. #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
  432. #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
  433. #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
  434. #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
  435. #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
  436. #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
  437. #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
  438. #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
  439. #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
  440. #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
  441. #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
  442. #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
  443. #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
  444. #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
  445. #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
  446. #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
  447. #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
  448. #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
  449. #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
  450. #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
  451. #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
  452. #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
  453. #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
  454. #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
  455. #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
  456. #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
  457. #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
  458. #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
  459. #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
  460. #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
  461. #define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */
  462. #define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */
  463. #define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */
  464. #define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */
  465. #define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */
  466. #define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */
  467. #define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */
  468. #define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */
  469. #define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */
  470. #define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */
  471. /* e500 definitions */
  472. #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
  473. #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
  474. #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
  475. #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
  476. #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
  477. #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
  478. #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
  479. #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
  480. #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
  481. #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
  482. #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
  483. #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
  484. #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
  485. #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
  486. #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
  487. #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
  488. #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */
  489. #define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */
  490. #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
  491. #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
  492. #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
  493. #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
  494. #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
  495. #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
  496. #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
  497. #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
  498. #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
  499. /* e6500 */
  500. #define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */
  501. #define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */
  502. #define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */
  503. #define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */
  504. #define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE
  505. #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
  506. #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
  507. #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
  508. #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
  509. #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
  510. #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
  511. #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
  512. #define TLBnCFG_NENTRY_MASK 0x00000fff
  513. #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
  514. #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
  515. #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
  516. #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
  517. #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
  518. #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
  519. #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
  520. #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
  521. #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
  522. #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
  523. #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
  524. #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
  525. #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
  526. #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
  527. #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
  528. #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
  529. #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
  530. #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
  531. #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
  532. #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
  533. #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
  534. #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
  535. #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
  536. #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
  537. #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
  538. #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
  539. #define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
  540. #define BUCSR_LS_EN 0x00400000 /* Link stack enable */
  541. #define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
  542. #define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
  543. #define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
  544. #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
  545. #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
  546. #define SPRN_PID1 0x279 /* Process ID Register 1 */
  547. #define SPRN_PID2 0x27a /* Process ID Register 2 */
  548. #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
  549. #define SPRN_MCAR 0x23d /* Machine Check Address register */
  550. #define MCSR_MCS 0x80000000 /* Machine Check Summary */
  551. #define MCSR_IB 0x40000000 /* Instruction PLB Error */
  552. #if defined(CONFIG_440)
  553. #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
  554. #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
  555. #else
  556. #define MCSR_DB 0x20000000 /* Data PLB Error */
  557. #endif /* defined(CONFIG_440) */
  558. #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
  559. #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
  560. #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
  561. #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
  562. #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
  563. #define ESR_ST 0x00800000 /* Store Operation */
  564. #if defined(CONFIG_MPC86xx)
  565. #define SPRN_MSSCR0 0x3f6
  566. #define SPRN_MSSSR0 0x3f7
  567. #endif
  568. #define SPRN_HDBCR0 0x3d0
  569. #define SPRN_HDBCR1 0x3d1
  570. #define SPRN_HDBCR2 0x3d2
  571. #define SPRN_HDBCR3 0x3d3
  572. #define SPRN_HDBCR4 0x3d4
  573. #define SPRN_HDBCR5 0x3d5
  574. #define SPRN_HDBCR6 0x3d6
  575. #define SPRN_HDBCR7 0x277
  576. #define SPRN_HDBCR8 0x278
  577. /* Short-hand versions for a number of the above SPRNs */
  578. #define CTR SPRN_CTR /* Counter Register */
  579. #define DAR SPRN_DAR /* Data Address Register */
  580. #define DABR SPRN_DABR /* Data Address Breakpoint Register */
  581. #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
  582. #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
  583. #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
  584. #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
  585. #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
  586. #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
  587. #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
  588. #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
  589. #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
  590. #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
  591. #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
  592. #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
  593. #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
  594. #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
  595. #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
  596. #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
  597. #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
  598. #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
  599. #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
  600. #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
  601. #define DBSR SPRN_DBSR /* Debug Status Register */
  602. #define DCMP SPRN_DCMP /* Data TLB Compare Register */
  603. #define DEC SPRN_DEC /* Decrement Register */
  604. #define DMISS SPRN_DMISS /* Data TLB Miss Register */
  605. #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
  606. #define EAR SPRN_EAR /* External Address Register */
  607. #define ESR SPRN_ESR /* Exception Syndrome Register */
  608. #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
  609. #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
  610. #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
  611. #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
  612. #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
  613. #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
  614. #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
  615. #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
  616. #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
  617. #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
  618. #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
  619. #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
  620. #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
  621. #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
  622. #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
  623. #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
  624. #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
  625. #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
  626. #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
  627. #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
  628. #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
  629. #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
  630. #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
  631. #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
  632. #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
  633. #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
  634. #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
  635. #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
  636. #define LR SPRN_LR
  637. #define MBAR SPRN_MBAR /* System memory base address */
  638. #if defined(CONFIG_MPC86xx)
  639. #define MSSCR0 SPRN_MSSCR0
  640. #endif
  641. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  642. #define PIR SPRN_PIR
  643. #endif
  644. #define SVR SPRN_SVR /* System-On-Chip Version Register */
  645. #define PVR SPRN_PVR /* Processor Version */
  646. #define RPA SPRN_RPA /* Required Physical Address Register */
  647. #define SDR1 SPRN_SDR1 /* MMU hash base register */
  648. #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
  649. #define SPR1 SPRN_SPRG1
  650. #define SPR2 SPRN_SPRG2
  651. #define SPR3 SPRN_SPRG3
  652. #define SPRG0 SPRN_SPRG0
  653. #define SPRG1 SPRN_SPRG1
  654. #define SPRG2 SPRN_SPRG2
  655. #define SPRG3 SPRN_SPRG3
  656. #define SPRG4 SPRN_SPRG4
  657. #define SPRG5 SPRN_SPRG5
  658. #define SPRG6 SPRN_SPRG6
  659. #define SPRG7 SPRN_SPRG7
  660. #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
  661. #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
  662. #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
  663. #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
  664. #define SVR SPRN_SVR /* System Version Register */
  665. #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
  666. #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
  667. #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
  668. #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
  669. #define TCR SPRN_TCR /* Timer Control Register */
  670. #define TSR SPRN_TSR /* Timer Status Register */
  671. #define ICTC 1019
  672. #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
  673. #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
  674. #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
  675. #define XER SPRN_XER
  676. #define DECAR SPRN_DECAR
  677. #define CSRR0 SPRN_CSRR0
  678. #define CSRR1 SPRN_CSRR1
  679. #define IVPR SPRN_IVPR
  680. #define USPRG0 SPRN_USPRG
  681. #define SPRG4R SPRN_SPRG4R
  682. #define SPRG5R SPRN_SPRG5R
  683. #define SPRG6R SPRN_SPRG6R
  684. #define SPRG7R SPRN_SPRG7R
  685. #define SPRG4W SPRN_SPRG4W
  686. #define SPRG5W SPRN_SPRG5W
  687. #define SPRG6W SPRN_SPRG6W
  688. #define SPRG7W SPRN_SPRG7W
  689. #define DEAR SPRN_DEAR
  690. #define DBCR2 SPRN_DBCR2
  691. #define IAC3 SPRN_IAC3
  692. #define IAC4 SPRN_IAC4
  693. #define DVC1 SPRN_DVC1
  694. #define DVC2 SPRN_DVC2
  695. #define IVOR0 SPRN_IVOR0
  696. #define IVOR1 SPRN_IVOR1
  697. #define IVOR2 SPRN_IVOR2
  698. #define IVOR3 SPRN_IVOR3
  699. #define IVOR4 SPRN_IVOR4
  700. #define IVOR5 SPRN_IVOR5
  701. #define IVOR6 SPRN_IVOR6
  702. #define IVOR7 SPRN_IVOR7
  703. #define IVOR8 SPRN_IVOR8
  704. #define IVOR9 SPRN_IVOR9
  705. #define IVOR10 SPRN_IVOR10
  706. #define IVOR11 SPRN_IVOR11
  707. #define IVOR12 SPRN_IVOR12
  708. #define IVOR13 SPRN_IVOR13
  709. #define IVOR14 SPRN_IVOR14
  710. #define IVOR15 SPRN_IVOR15
  711. #define IVOR32 SPRN_IVOR32
  712. #define IVOR33 SPRN_IVOR33
  713. #define IVOR34 SPRN_IVOR34
  714. #define IVOR35 SPRN_IVOR35
  715. #define MCSRR0 SPRN_MCSRR0
  716. #define MCSRR1 SPRN_MCSRR1
  717. #define L1CSR0 SPRN_L1CSR0
  718. #define L1CSR1 SPRN_L1CSR1
  719. #define L1CSR2 SPRN_L1CSR2
  720. #define L1CFG0 SPRN_L1CFG0
  721. #define L1CFG1 SPRN_L1CFG1
  722. #define L2CFG0 SPRN_L2CFG0
  723. #define L2CSR0 SPRN_L2CSR0
  724. #define L2CSR1 SPRN_L2CSR1
  725. #define MCSR SPRN_MCSR
  726. #define MMUCSR0 SPRN_MMUCSR0
  727. #define BUCSR SPRN_BUCSR
  728. #define PID0 SPRN_PID
  729. #define PID1 SPRN_PID1
  730. #define PID2 SPRN_PID2
  731. #define MAS0 SPRN_MAS0
  732. #define MAS1 SPRN_MAS1
  733. #define MAS2 SPRN_MAS2
  734. #define MAS3 SPRN_MAS3
  735. #define MAS4 SPRN_MAS4
  736. #define MAS5 SPRN_MAS5
  737. #define MAS6 SPRN_MAS6
  738. #define MAS7 SPRN_MAS7
  739. #define MAS8 SPRN_MAS8
  740. #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
  741. #define DAR_DEAR DEAR
  742. #else
  743. #define DAR_DEAR DAR
  744. #endif
  745. /* Device Control Registers */
  746. #define DCRN_BEAR 0x090 /* Bus Error Address Register */
  747. #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
  748. #define BESR_DSES 0x80000000 /* Data-Side Error Status */
  749. #define BESR_DMES 0x40000000 /* DMA Error Status */
  750. #define BESR_RWS 0x20000000 /* Read/Write Status */
  751. #define BESR_ETMASK 0x1C000000 /* Error Type */
  752. #define ET_PROT 0
  753. #define ET_PARITY 1
  754. #define ET_NCFG 2
  755. #define ET_BUSERR 4
  756. #define ET_BUSTO 6
  757. #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
  758. #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
  759. #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
  760. #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
  761. #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
  762. #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
  763. #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
  764. #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
  765. #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
  766. #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
  767. #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
  768. #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
  769. #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
  770. #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
  771. #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
  772. #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
  773. #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
  774. #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
  775. #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
  776. #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
  777. #define DCRN_DMASR 0x0E0 /* DMA Status Register */
  778. #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
  779. #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
  780. #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
  781. #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
  782. #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
  783. #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
  784. #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
  785. #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
  786. #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
  787. #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
  788. #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
  789. #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
  790. #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
  791. #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
  792. #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
  793. #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
  794. #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
  795. #define IOCR_E0TE 0x80000000
  796. #define IOCR_E0LP 0x40000000
  797. #define IOCR_E1TE 0x20000000
  798. #define IOCR_E1LP 0x10000000
  799. #define IOCR_E2TE 0x08000000
  800. #define IOCR_E2LP 0x04000000
  801. #define IOCR_E3TE 0x02000000
  802. #define IOCR_E3LP 0x01000000
  803. #define IOCR_E4TE 0x00800000
  804. #define IOCR_E4LP 0x00400000
  805. #define IOCR_EDT 0x00080000
  806. #define IOCR_SOR 0x00040000
  807. #define IOCR_EDO 0x00008000
  808. #define IOCR_2XC 0x00004000
  809. #define IOCR_ATC 0x00002000
  810. #define IOCR_SPD 0x00001000
  811. #define IOCR_BEM 0x00000800
  812. #define IOCR_PTD 0x00000400
  813. #define IOCR_ARE 0x00000080
  814. #define IOCR_DRC 0x00000020
  815. #define IOCR_RDM(x) (((x) & 0x3) << 3)
  816. #define IOCR_TCS 0x00000004
  817. #define IOCR_SCS 0x00000002
  818. #define IOCR_SPC 0x00000001
  819. /* System-On-Chip Version Register */
  820. /* System-On-Chip Version Register (SVR) field extraction */
  821. #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
  822. #define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */
  823. #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
  824. #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
  825. #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
  826. #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
  827. #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
  828. #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
  829. #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
  830. /* Processor Version Register */
  831. /* Processor Version Register (PVR) field extraction */
  832. #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
  833. #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
  834. /*
  835. * AMCC has further subdivided the standard PowerPC 16-bit version and
  836. * revision subfields of the PVR for the PowerPC 403s into the following:
  837. */
  838. #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
  839. #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
  840. #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
  841. #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
  842. #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
  843. #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
  844. /* e600 core PVR fields */
  845. #define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
  846. #define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
  847. #define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
  848. #define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
  849. /* Processor Version Numbers */
  850. #define PVR_403GA 0x00200000
  851. #define PVR_403GB 0x00200100
  852. #define PVR_403GC 0x00200200
  853. #define PVR_403GCX 0x00201400
  854. #define PVR_405GP 0x40110000
  855. #define PVR_405GP_RB 0x40110040
  856. #define PVR_405GP_RC 0x40110082
  857. #define PVR_405GP_RD 0x401100C4
  858. #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
  859. #define PVR_405EP_RA 0x51210950
  860. #define PVR_405GPR_RB 0x50910951
  861. #define PVR_405EZ_RA 0x41511460
  862. #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
  863. #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
  864. #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
  865. #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
  866. #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
  867. #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
  868. #define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
  869. #define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
  870. #define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */
  871. #define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */
  872. #define PVR_440GP_RB 0x40120440
  873. #define PVR_440GP_RC 0x40120481
  874. #define PVR_440EP_RA 0x42221850
  875. #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
  876. #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
  877. #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
  878. #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
  879. #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
  880. #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
  881. #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
  882. #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
  883. #define PVR_440GX_RA 0x51B21850
  884. #define PVR_440GX_RB 0x51B21851
  885. #define PVR_440GX_RC 0x51B21892
  886. #define PVR_440GX_RF 0x51B21894
  887. #define PVR_405EP_RB 0x51210950
  888. #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
  889. #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
  890. #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
  891. #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
  892. #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
  893. #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
  894. #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
  895. #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
  896. #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
  897. #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
  898. #define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
  899. #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
  900. #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
  901. #define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
  902. #define PVR_460SX_RA 0x13541800 /* 460SX rev A */
  903. #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
  904. #define PVR_460GX_RA 0x13541802 /* 460GX rev A */
  905. #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
  906. #define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
  907. #define PVR_601 0x00010000
  908. #define PVR_602 0x00050000
  909. #define PVR_603 0x00030000
  910. #define PVR_603e 0x00060000
  911. #define PVR_603ev 0x00070000
  912. #define PVR_603r 0x00071000
  913. #define PVR_604 0x00040000
  914. #define PVR_604e 0x00090000
  915. #define PVR_604r 0x000A0000
  916. #define PVR_620 0x00140000
  917. #define PVR_740 0x00080000
  918. #define PVR_750 PVR_740
  919. #define PVR_740P 0x10080000
  920. #define PVR_750P PVR_740P
  921. #define PVR_7400 0x000C0000
  922. #define PVR_7410 0x800C0000
  923. #define PVR_7450 0x80000000
  924. #define PVR_85xx 0x80200000
  925. #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
  926. #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
  927. #define PVR_VER_E500_V1 0x8020
  928. #define PVR_VER_E500_V2 0x8021
  929. #define PVR_VER_E500MC 0x8023
  930. #define PVR_VER_E5500 0x8024
  931. #define PVR_VER_E6500 0x8040
  932. #define PVR_86xx 0x80040000
  933. #define PVR_VIRTEX5 0x7ff21912
  934. /*
  935. * For the 8xx processors, all of them report the same PVR family for
  936. * the PowerPC core. The various versions of these processors must be
  937. * differentiated by the version number in the Communication Processor
  938. * Module (CPM).
  939. */
  940. #define PVR_821 0x00500000
  941. #define PVR_823 PVR_821
  942. #define PVR_850 PVR_821
  943. #define PVR_860 PVR_821
  944. #define PVR_7400 0x000C0000
  945. #define PVR_8240 0x00810100
  946. /*
  947. * PowerQUICC II family processors report different PVR values depending
  948. * on silicon process (HiP3, HiP4, HiP7, etc.)
  949. */
  950. #define PVR_8260 PVR_8240
  951. #define PVR_8260_HIP3 0x00810101
  952. #define PVR_8260_HIP4 0x80811014
  953. #define PVR_8260_HIP7 0x80822011
  954. #define PVR_8260_HIP7R1 0x80822013
  955. #define PVR_8260_HIP7RA 0x80822014
  956. /*
  957. * MPC 52xx
  958. */
  959. #define PVR_5200 0x80822011
  960. #define PVR_5200B 0x80822014
  961. /*
  962. * 405EX/EXr CHIP_21 Errata
  963. */
  964. #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
  965. #define CONFIG_SYS_4xx_CHIP_21_ERRATA
  966. #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
  967. #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
  968. #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
  969. #endif
  970. #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
  971. #define CONFIG_SYS_4xx_CHIP_21_ERRATA
  972. #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
  973. #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
  974. #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
  975. #endif
  976. #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
  977. #define CONFIG_SYS_4xx_CHIP_21_ERRATA
  978. #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
  979. #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
  980. #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
  981. #endif
  982. #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
  983. #define CONFIG_SYS_4xx_CHIP_21_ERRATA
  984. #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
  985. #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
  986. #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
  987. #endif
  988. /*
  989. * System Version Register
  990. */
  991. /* System Version Register (SVR) field extraction */
  992. #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
  993. #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
  994. #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
  995. #ifdef CONFIG_ARCH_MPC8536
  996. #define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
  997. #else
  998. #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
  999. #endif
  1000. #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
  1001. /* Some parts define SVR[0:23] as the SOC version */
  1002. #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
  1003. /* whether MPC8xxxE (i.e. has SEC) */
  1004. #if defined(CONFIG_MPC85xx)
  1005. #define IS_E_PROCESSOR(svr) (svr & 0x80000)
  1006. #else
  1007. #if defined(CONFIG_MPC83xx)
  1008. #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
  1009. #endif
  1010. #endif
  1011. #define IS_SVR_REV(svr, maj, min) \
  1012. ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
  1013. /*
  1014. * SVR_SOC_VER() Version Values
  1015. */
  1016. #define SVR_8533 0x803400
  1017. #define SVR_8535 0x803701
  1018. #define SVR_8536 0x803700
  1019. #define SVR_8540 0x803000
  1020. #define SVR_8541 0x807200
  1021. #define SVR_8543 0x803200
  1022. #define SVR_8544 0x803401
  1023. #define SVR_8545 0x803102
  1024. #define SVR_8547 0x803101
  1025. #define SVR_8548 0x803100
  1026. #define SVR_8555 0x807100
  1027. #define SVR_8560 0x807000
  1028. #define SVR_8567 0x807501
  1029. #define SVR_8568 0x807500
  1030. #define SVR_8569 0x808000
  1031. #define SVR_8572 0x80E000
  1032. #define SVR_P1010 0x80F100
  1033. #define SVR_P1011 0x80E500
  1034. #define SVR_P1012 0x80E501
  1035. #define SVR_P1013 0x80E700
  1036. #define SVR_P1014 0x80F101
  1037. #define SVR_P1017 0x80F700
  1038. #define SVR_P1020 0x80E400
  1039. #define SVR_P1021 0x80E401
  1040. #define SVR_P1022 0x80E600
  1041. #define SVR_P1023 0x80F600
  1042. #define SVR_P1024 0x80E402
  1043. #define SVR_P1025 0x80E403
  1044. #define SVR_P2010 0x80E300
  1045. #define SVR_P2020 0x80E200
  1046. #define SVR_P2040 0x821000
  1047. #define SVR_P2041 0x821001
  1048. #define SVR_P3041 0x821103
  1049. #define SVR_P4040 0x820100
  1050. #define SVR_P4080 0x820000
  1051. #define SVR_P5010 0x822100
  1052. #define SVR_P5020 0x822000
  1053. #define SVR_P5021 0X820500
  1054. #define SVR_P5040 0x820400
  1055. #define SVR_T4240 0x824000
  1056. #define SVR_T4120 0x824001
  1057. #define SVR_T4160 0x824100
  1058. #define SVR_T4080 0x824102
  1059. #define SVR_C291 0x850000
  1060. #define SVR_C292 0x850020
  1061. #define SVR_C293 0x850030
  1062. #define SVR_B4860 0X868000
  1063. #define SVR_G4860 0x868001
  1064. #define SVR_B4460 0x868003
  1065. #define SVR_B4440 0x868100
  1066. #define SVR_G4440 0x868101
  1067. #define SVR_B4420 0x868102
  1068. #define SVR_B4220 0x868103
  1069. #define SVR_T1040 0x852000
  1070. #define SVR_T1041 0x852001
  1071. #define SVR_T1042 0x852002
  1072. #define SVR_T1020 0x852100
  1073. #define SVR_T1021 0x852101
  1074. #define SVR_T1022 0x852102
  1075. #define SVR_T1024 0x854000
  1076. #define SVR_T1023 0x854100
  1077. #define SVR_T1014 0x854400
  1078. #define SVR_T1013 0x854500
  1079. #define SVR_T2080 0x853000
  1080. #define SVR_T2081 0x853100
  1081. #define SVR_8610 0x80A000
  1082. #define SVR_8641 0x809000
  1083. #define SVR_8641D 0x809001
  1084. #define SVR_9130 0x860001
  1085. #define SVR_9131 0x860000
  1086. #define SVR_9132 0x861000
  1087. #define SVR_9232 0x861400
  1088. #define SVR_Unknown 0xFFFFFF
  1089. #define _GLOBAL(n)\
  1090. .globl n;\
  1091. n:
  1092. /* Macros for setting and retrieving special purpose registers */
  1093. #define stringify(s) tostring(s)
  1094. #define tostring(s) #s
  1095. #define mfdcr(rn) ({unsigned int rval; \
  1096. asm volatile("mfdcr %0," stringify(rn) \
  1097. : "=r" (rval)); rval;})
  1098. #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
  1099. #define mfmsr() ({unsigned int rval; \
  1100. asm volatile("mfmsr %0" : "=r" (rval)); rval;})
  1101. #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
  1102. #define mfspr(rn) ({unsigned int rval; \
  1103. asm volatile("mfspr %0," stringify(rn) \
  1104. : "=r" (rval)); rval;})
  1105. #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
  1106. #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
  1107. /* Segment Registers */
  1108. #define SR0 0
  1109. #define SR1 1
  1110. #define SR2 2
  1111. #define SR3 3
  1112. #define SR4 4
  1113. #define SR5 5
  1114. #define SR6 6
  1115. #define SR7 7
  1116. #define SR8 8
  1117. #define SR9 9
  1118. #define SR10 10
  1119. #define SR11 11
  1120. #define SR12 12
  1121. #define SR13 13
  1122. #define SR14 14
  1123. #define SR15 15
  1124. #ifndef __ASSEMBLY__
  1125. struct cpu_type {
  1126. char name[15];
  1127. u32 soc_ver;
  1128. u32 num_cores;
  1129. u32 mask; /* which cpu(s) actually exist */
  1130. #ifdef CONFIG_HETROGENOUS_CLUSTERS
  1131. u32 dsp_num_cores;
  1132. u32 dsp_mask; /* which DSP cpu(s) actually exist */
  1133. #endif
  1134. };
  1135. struct cpu_type *identify_cpu(u32 ver);
  1136. int fixup_cpu(void);
  1137. int fsl_qoriq_core_to_cluster(unsigned int core);
  1138. int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
  1139. #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
  1140. #define CPU_TYPE_ENTRY(n, v, nc) \
  1141. { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
  1142. .mask = (1 << (nc)) - 1 }
  1143. #define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
  1144. { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
  1145. #else
  1146. #if defined(CONFIG_MPC83xx)
  1147. #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
  1148. #endif
  1149. #endif
  1150. #ifndef CONFIG_MACH_SPECIFIC
  1151. extern int _machine;
  1152. extern int have_of;
  1153. #endif /* CONFIG_MACH_SPECIFIC */
  1154. /* what kind of prep workstation we are */
  1155. extern int _prep_type;
  1156. /*
  1157. * This is used to identify the board type from a given PReP board
  1158. * vendor. Board revision is also made available.
  1159. */
  1160. extern unsigned char ucSystemType;
  1161. extern unsigned char ucBoardRev;
  1162. extern unsigned char ucBoardRevMaj, ucBoardRevMin;
  1163. struct task_struct;
  1164. void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
  1165. void release_thread(struct task_struct *);
  1166. /*
  1167. * Create a new kernel thread.
  1168. */
  1169. extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
  1170. /*
  1171. * Bus types
  1172. */
  1173. #define EISA_bus 0
  1174. #define EISA_bus__is_a_macro /* for versions in ksyms.c */
  1175. #define MCA_bus 0
  1176. #define MCA_bus__is_a_macro /* for versions in ksyms.c */
  1177. /* Lazy FPU handling on uni-processor */
  1178. extern struct task_struct *last_task_used_math;
  1179. extern struct task_struct *last_task_used_altivec;
  1180. /*
  1181. * this is the minimum allowable io space due to the location
  1182. * of the io areas on prep (first one at 0x80000000) but
  1183. * as soon as I get around to remapping the io areas with the BATs
  1184. * to match the mac we can raise this. -- Cort
  1185. */
  1186. #define TASK_SIZE (0x80000000UL)
  1187. /* This decides where the kernel will search for a free chunk of vm
  1188. * space during mmap's.
  1189. */
  1190. #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
  1191. typedef struct {
  1192. unsigned long seg;
  1193. } mm_segment_t;
  1194. struct thread_struct {
  1195. unsigned long ksp; /* Kernel stack pointer */
  1196. unsigned long wchan; /* Event task is sleeping on */
  1197. struct pt_regs *regs; /* Pointer to saved register state */
  1198. mm_segment_t fs; /* for get_fs() validation */
  1199. void *pgdir; /* root of page-table tree */
  1200. signed long last_syscall;
  1201. double fpr[32]; /* Complete floating point set */
  1202. unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
  1203. unsigned long fpscr; /* Floating point status */
  1204. #ifdef CONFIG_ALTIVEC
  1205. vector128 vr[32]; /* Complete AltiVec set */
  1206. vector128 vscr; /* AltiVec status */
  1207. unsigned long vrsave;
  1208. #endif /* CONFIG_ALTIVEC */
  1209. };
  1210. #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
  1211. #define INIT_THREAD { \
  1212. INIT_SP, /* ksp */ \
  1213. 0, /* wchan */ \
  1214. (struct pt_regs *)INIT_SP - 1, /* regs */ \
  1215. KERNEL_DS, /*fs*/ \
  1216. swapper_pg_dir, /* pgdir */ \
  1217. 0, /* last_syscall */ \
  1218. {0}, 0, 0 \
  1219. }
  1220. /*
  1221. * Note: the vm_start and vm_end fields here should *not*
  1222. * be in kernel space. (Could vm_end == vm_start perhaps?)
  1223. */
  1224. #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
  1225. PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
  1226. 1, NULL, NULL }
  1227. /*
  1228. * Return saved PC of a blocked thread. For now, this is the "user" PC
  1229. */
  1230. static inline unsigned long thread_saved_pc(struct thread_struct *t)
  1231. {
  1232. return (t->regs) ? t->regs->nip : 0;
  1233. }
  1234. #define copy_segments(tsk, mm) do { } while (0)
  1235. #define release_segments(mm) do { } while (0)
  1236. #define forget_segments() do { } while (0)
  1237. unsigned long get_wchan(struct task_struct *p);
  1238. #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
  1239. #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
  1240. /*
  1241. * NOTE! The task struct and the stack go together
  1242. */
  1243. #define THREAD_SIZE (2*PAGE_SIZE)
  1244. #define alloc_task_struct() \
  1245. ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
  1246. #define free_task_struct(p) free_pages((unsigned long)(p),1)
  1247. #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
  1248. /* in process.c - for early bootup debug -- Cort */
  1249. int ll_printk(const char *, ...);
  1250. void ll_puts(const char *);
  1251. #define init_task (init_task_union.task)
  1252. #define init_stack (init_task_union.stack)
  1253. /* In misc.c */
  1254. void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
  1255. int prt_83xx_rsr(void);
  1256. int prt_8260_rsr(void);
  1257. int prt_8260_clks(void);
  1258. #endif /* ndef ASSEMBLY*/
  1259. #ifdef CONFIG_MACH_SPECIFIC
  1260. #if defined(CONFIG_WALNUT)
  1261. #define _machine _MACH_walnut
  1262. #define have_of 0
  1263. #elif defined(CONFIG_MPC8260)
  1264. #define _machine _MACH_8260
  1265. #define have_of 0
  1266. #else
  1267. #error "Machine not defined correctly"
  1268. #endif
  1269. #endif /* CONFIG_MACH_SPECIFIC */
  1270. #if defined(CONFIG_MPC85xx) || defined(CONFIG_440)
  1271. #define EPAPR_MAGIC (0x45504150)
  1272. #else
  1273. #define EPAPR_MAGIC (0x65504150)
  1274. #endif
  1275. #endif /* __ASM_PPC_PROCESSOR_H */