cache.h 2.0 KB

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  1. /*
  2. * include/asm-ppc/cache.h
  3. */
  4. #ifndef __ARCH_PPC_CACHE_H
  5. #define __ARCH_PPC_CACHE_H
  6. #include <asm/processor.h>
  7. /* bytes per L1 cache line */
  8. #if defined(CONFIG_PPC64BRIDGE)
  9. #define L1_CACHE_SHIFT 7
  10. #elif defined(CONFIG_E500MC)
  11. #define L1_CACHE_SHIFT 6
  12. #else
  13. #define L1_CACHE_SHIFT 5
  14. #endif
  15. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  16. /*
  17. * Use the L1 data cache line size value for the minimum DMA buffer alignment
  18. * on PowerPC.
  19. */
  20. #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
  21. /*
  22. * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
  23. */
  24. #ifndef CONFIG_SYS_CACHELINE_SIZE
  25. #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
  26. #endif
  27. #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  28. #define L1_CACHE_PAGES 8
  29. #define SMP_CACHE_BYTES L1_CACHE_BYTES
  30. #ifdef MODULE
  31. #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
  32. #else
  33. #define __cacheline_aligned \
  34. __attribute__((__aligned__(L1_CACHE_BYTES), \
  35. __section__(".data.cacheline_aligned")))
  36. #endif
  37. #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  38. extern void flush_dcache_range(unsigned long start, unsigned long stop);
  39. extern void clean_dcache_range(unsigned long start, unsigned long stop);
  40. extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
  41. extern void flush_dcache(void);
  42. extern void invalidate_dcache(void);
  43. extern void invalidate_icache(void);
  44. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  45. extern void unlock_ram_in_cache(void);
  46. #endif /* CONFIG_SYS_INIT_RAM_LOCK */
  47. #endif /* __ASSEMBLY__ */
  48. #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  49. int l2cache_init(void);
  50. void enable_cpc(void);
  51. void disable_cpc_sram(void);
  52. #endif
  53. /* prep registers for L2 */
  54. #define CACHECRBA 0x80000823 /* Cache configuration register address */
  55. #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
  56. #define L2CACHE_512KB 0x00 /* 512KB */
  57. #define L2CACHE_256KB 0x01 /* 256KB */
  58. #define L2CACHE_1MB 0x02 /* 1MB */
  59. #define L2CACHE_NONE 0x03 /* NONE */
  60. #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
  61. #endif