4xx_uart.c 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267
  1. /*
  2. * (C) Copyright 2000-2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2010
  6. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0 IBM-pibs
  9. */
  10. #include <common.h>
  11. #include <asm/processor.h>
  12. #include <asm/io.h>
  13. #include <watchdog.h>
  14. #include <asm/ppc4xx.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #if defined(CONFIG_405GP) || \
  17. defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
  18. defined(CONFIG_405EX) || defined(CONFIG_440)
  19. #if defined(CONFIG_440)
  20. #if defined(CONFIG_440GP)
  21. #define CR0_MASK 0x3fff0000
  22. #define CR0_EXTCLK_ENA 0x00600000
  23. #define CR0_UDIV_POS 16
  24. #define UDIV_SUBTRACT 1
  25. #define UART0_SDR CPC0_CR0
  26. #define MFREG(a, d) d = mfdcr(a)
  27. #define MTREG(a, d) mtdcr(a, d)
  28. #else /* #if defined(CONFIG_440GP) */
  29. /* all other 440 PPC's access clock divider via sdr register */
  30. #define CR0_MASK 0xdfffffff
  31. #define CR0_EXTCLK_ENA 0x00800000
  32. #define CR0_UDIV_POS 0
  33. #define UDIV_SUBTRACT 0
  34. #define UART0_SDR SDR0_UART0
  35. #define UART1_SDR SDR0_UART1
  36. #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  37. defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  38. defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  39. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  40. #define UART2_SDR SDR0_UART2
  41. #endif
  42. #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
  43. defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
  44. defined(CONFIG_460EX) || defined(CONFIG_460GT)
  45. #define UART3_SDR SDR0_UART3
  46. #endif
  47. #define MFREG(a, d) mfsdr(a, d)
  48. #define MTREG(a, d) mtsdr(a, d)
  49. #endif /* #if defined(CONFIG_440GP) */
  50. #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  51. #define UCR0_MASK 0x0000007f
  52. #define UCR1_MASK 0x00007f00
  53. #define UCR0_UDIV_POS 0
  54. #define UCR1_UDIV_POS 8
  55. #define UDIV_MAX 127
  56. #elif defined(CONFIG_405EX)
  57. #define MFREG(a, d) mfsdr(a, d)
  58. #define MTREG(a, d) mtsdr(a, d)
  59. #define CR0_MASK 0x000000ff
  60. #define CR0_EXTCLK_ENA 0x00800000
  61. #define CR0_UDIV_POS 0
  62. #define UDIV_SUBTRACT 0
  63. #define UART0_SDR SDR0_UART0
  64. #define UART1_SDR SDR0_UART1
  65. #else /* CONFIG_405GP */
  66. #define CR0_MASK 0x00001fff
  67. #define CR0_EXTCLK_ENA 0x000000c0
  68. #define CR0_UDIV_POS 1
  69. #define UDIV_MAX 32
  70. #endif
  71. #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  72. #error "External serial clock not supported on AMCC PPC405EP!"
  73. #endif
  74. #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
  75. defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  76. /*
  77. * For some SoC's, the cpu clock is on divider chain A, UART on
  78. * divider chain B ... so cpu clock is irrelevant. Get the
  79. * "optimized" values that are subject to the 1/2 opb clock
  80. * constraint.
  81. */
  82. static u16 serial_bdiv(int baudrate, u32 *udiv)
  83. {
  84. sys_info_t sysinfo;
  85. u32 div; /* total divisor udiv * bdiv */
  86. u32 umin; /* minimum udiv */
  87. u16 diff; /* smallest diff */
  88. u16 idiff; /* current diff */
  89. u16 ibdiv; /* current bdiv */
  90. u32 i;
  91. u32 est; /* current estimate */
  92. u32 max;
  93. #if defined(CONFIG_405EZ)
  94. u32 cpr_pllc;
  95. u32 plloutb;
  96. u32 reg;
  97. #endif
  98. get_sys_info(&sysinfo);
  99. #if defined(CONFIG_405EZ)
  100. /* check the pll feedback source */
  101. mfcpr(CPR0_PLLC, cpr_pllc);
  102. plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
  103. sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
  104. sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
  105. div = plloutb / (16 * baudrate); /* total divisor */
  106. umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
  107. max = 256; /* highest possible */
  108. #else /* 405EZ */
  109. div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
  110. umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
  111. max = 32; /* highest possible */
  112. #endif /* 405EZ */
  113. *udiv = diff = max;
  114. /*
  115. * i is the test udiv value -- start with the largest
  116. * possible (max) to minimize serial clock and constrain
  117. * search to umin.
  118. */
  119. for (i = max; i > umin; i--) {
  120. ibdiv = div / i;
  121. est = i * ibdiv;
  122. idiff = (est > div) ? (est - div) : (div - est);
  123. if (idiff == 0) {
  124. *udiv = i;
  125. break; /* can't do better */
  126. } else if (idiff < diff) {
  127. *udiv = i; /* best so far */
  128. diff = idiff; /* update lowest diff*/
  129. }
  130. }
  131. #if defined(CONFIG_405EZ)
  132. mfcpr(CPR0_PERD0, reg);
  133. reg &= ~0x0000ffff;
  134. reg |= ((*udiv - 0) << 8) | (*udiv - 0);
  135. mtcpr(CPR0_PERD0, reg);
  136. #endif
  137. return div / *udiv;
  138. }
  139. #endif /* #if (defined(CONFIG_405EP) ... */
  140. /*
  141. * This function returns the UART clock used by the common
  142. * NS16550 driver. Additionally the SoC internal divisors for
  143. * optimal UART baudrate are configured.
  144. */
  145. int get_serial_clock(void)
  146. {
  147. u32 clk;
  148. u32 udiv;
  149. #if !defined(CONFIG_405EZ)
  150. u32 reg;
  151. #endif
  152. #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
  153. PPC4xx_SYS_INFO sys_info;
  154. #endif
  155. /*
  156. * Programming of the internal divisors is SoC specific.
  157. * Let's handle this in some #ifdef's for the SoC's.
  158. */
  159. #if defined(CONFIG_405GP)
  160. reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
  161. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  162. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  163. udiv = 1;
  164. reg |= CR0_EXTCLK_ENA;
  165. #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  166. clk = gd->cpu_clk;
  167. #ifdef CONFIG_SYS_405_UART_ERRATA_59
  168. udiv = 31; /* Errata 59: stuck at 31 */
  169. #else /* CONFIG_SYS_405_UART_ERRATA_59 */
  170. {
  171. u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
  172. udiv = (clk + tmp / 2) / tmp;
  173. }
  174. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  175. udiv = UDIV_MAX;
  176. #endif /* CONFIG_SYS_405_UART_ERRATA_59 */
  177. #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  178. reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
  179. mtdcr (CPC0_CR0, reg);
  180. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  181. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  182. #else
  183. clk = CONFIG_SYS_BASE_BAUD * 16;
  184. #endif
  185. #endif
  186. #if defined(CONFIG_405EP)
  187. {
  188. u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
  189. reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
  190. clk = gd->cpu_clk;
  191. udiv = (clk + tmp / 2) / tmp;
  192. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  193. udiv = UDIV_MAX;
  194. }
  195. reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
  196. reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
  197. mtdcr(CPC0_UCR, reg);
  198. clk = CONFIG_SYS_BASE_BAUD * 16;
  199. #endif /* CONFIG_405EP */
  200. #if defined(CONFIG_405EX) || defined(CONFIG_440)
  201. MFREG(UART0_SDR, reg);
  202. reg &= ~CR0_MASK;
  203. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  204. reg |= CR0_EXTCLK_ENA;
  205. udiv = 1;
  206. clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  207. #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  208. clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
  209. #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
  210. reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
  211. /*
  212. * Configure input clock to baudrate generator for all
  213. * available serial ports here
  214. */
  215. MTREG(UART0_SDR, reg);
  216. #if defined(UART1_SDR)
  217. MTREG(UART1_SDR, reg);
  218. #endif
  219. #if defined(UART2_SDR)
  220. MTREG(UART2_SDR, reg);
  221. #endif
  222. #if defined(UART3_SDR)
  223. MTREG(UART3_SDR, reg);
  224. #endif
  225. #endif /* CONFIG_405EX ... */
  226. #if defined(CONFIG_405EZ)
  227. clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
  228. #endif /* CONFIG_405EZ */
  229. /*
  230. * Correct UART frequency in bd-info struct now that
  231. * the UART divisor is available
  232. */
  233. #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
  234. gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
  235. #else
  236. get_sys_info(&sys_info);
  237. gd->arch.uart_clk = sys_info.freqUART / udiv;
  238. #endif
  239. return clk;
  240. }
  241. #endif /* CONFIG_405GP */