CATcenter.h 27 KB

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  1. /*
  2. * ueberarbeitet durch Christoph Seyfert
  3. *
  4. * (C) Copyright 2004-2005 DENX Software Engineering,
  5. * Wolfgang Grandegger <wg@denx.de>
  6. * (C) Copyright 2003
  7. * DAVE Srl
  8. *
  9. * http://www.dave-tech.it
  10. * http://www.wawnet.biz
  11. * mailto:info@wawnet.biz
  12. *
  13. * Credits: Stefan Roese, Wolfgang Denk
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. /*
  31. * board/config.h - configuration options, board specific
  32. */
  33. #ifndef __CONFIG_H
  34. #define __CONFIG_H
  35. #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
  36. #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
  37. #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
  38. #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  39. #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  40. #endif
  41. /* Only one of the following two symbols must be defined (default is 25 MHz)
  42. * CONFIG_PPCHAMELEON_CLK_25
  43. * CONFIG_PPCHAMELEON_CLK_33
  44. */
  45. #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  46. #define CONFIG_PPCHAMELEON_CLK_25
  47. #endif
  48. #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  49. #error "* Two external frequencies (SysClk) are defined! *"
  50. #endif
  51. #undef CONFIG_PPCHAMELEON_SMI712
  52. /*
  53. * Debug stuff
  54. */
  55. #undef __DEBUG_START_FROM_SRAM__
  56. #define __DISABLE_MACHINE_EXCEPTION__
  57. #ifdef __DEBUG_START_FROM_SRAM__
  58. #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
  59. #endif
  60. /*
  61. * High Level Configuration Options
  62. * (easy to change)
  63. */
  64. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  65. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  66. #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
  67. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  68. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  69. #ifdef CONFIG_PPCHAMELEON_CLK_25
  70. # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  71. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  72. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  73. #else
  74. # error "* External frequency (SysClk) not defined! *"
  75. #endif
  76. #define CONFIG_UART1_CONSOLE 1 /* Use second UART */
  77. #define CONFIG_BAUDRATE 115200
  78. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  79. #define CONFIG_VERSION_VARIABLE 1 /* add version variable */
  80. #define CONFIG_IDENT_STRING "1"
  81. #undef CONFIG_BOOTARGS
  82. /* Ethernet stuff */
  83. #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  84. #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
  85. #define CONFIG_HAS_ETH1
  86. #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
  87. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  88. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  89. #undef CONFIG_EXT_PHY
  90. #define CONFIG_NET_MULTI 1
  91. #define CONFIG_MII 1 /* MII PHY management */
  92. #ifndef CONFIG_EXT_PHY
  93. #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
  94. #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
  95. #else
  96. #define CONFIG_PHY_ADDR 2 /* PHY address */
  97. #endif
  98. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  99. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  100. /*
  101. * BOOTP options
  102. */
  103. #define CONFIG_BOOTP_BOOTFILESIZE
  104. #define CONFIG_BOOTP_BOOTPATH
  105. #define CONFIG_BOOTP_GATEWAY
  106. #define CONFIG_BOOTP_HOSTNAME
  107. /*
  108. * Command line configuration.
  109. */
  110. #include <config_cmd_default.h>
  111. #define CONFIG_CMD_DHCP
  112. #define CONFIG_CMD_ELF
  113. #define CONFIG_CMD_EEPROM
  114. #define CONFIG_CMD_I2C
  115. #define CONFIG_CMD_IRQ
  116. #define CONFIG_CMD_JFFS2
  117. #define CONFIG_CMD_MII
  118. #define CONFIG_CMD_NAND
  119. #define CONFIG_CMD_NFS
  120. #define CONFIG_CMD_SNTP
  121. #define CONFIG_MAC_PARTITION
  122. #define CONFIG_DOS_PARTITION
  123. #undef CONFIG_WATCHDOG /* watchdog disabled */
  124. #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
  125. #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
  126. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  127. /*
  128. * Miscellaneous configurable options
  129. */
  130. #define CFG_LONGHELP /* undef to save memory */
  131. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  132. #define CFG_HUSH_PARSER /* use "hush" command parser */
  133. #ifdef CFG_HUSH_PARSER
  134. #define CFG_PROMPT_HUSH_PS2 "> "
  135. #endif
  136. #if defined(CONFIG_CMD_KGDB)
  137. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  138. #else
  139. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  140. #endif
  141. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  142. #define CFG_MAXARGS 16 /* max number of command args */
  143. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  144. #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
  145. #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  146. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  147. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  148. #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
  149. #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
  150. #define CFG_BASE_BAUD 691200
  151. /* The following table includes the supported baudrates */
  152. #define CFG_BAUDRATE_TABLE \
  153. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  154. 57600, 115200, 230400, 460800, 921600 }
  155. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  156. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  157. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  158. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  159. /*-----------------------------------------------------------------------
  160. * NAND-FLASH stuff
  161. *-----------------------------------------------------------------------
  162. */
  163. #define CFG_NAND0_BASE 0xFF400000
  164. #define CFG_NAND1_BASE 0xFF000000
  165. #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
  166. #define NAND_BIG_DELAY_US 25
  167. /* For CATcenter there is only NAND on the module */
  168. #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  169. #define SECTORSIZE 512
  170. #define NAND_NO_RB
  171. #define ADDR_COLUMN 1
  172. #define ADDR_PAGE 2
  173. #define ADDR_COLUMN_PAGE 3
  174. #define NAND_ChipID_UNKNOWN 0x00
  175. #define NAND_MAX_FLOORS 1
  176. #define NAND_MAX_CHIPS 1
  177. #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  178. #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  179. #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  180. #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  181. #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
  182. #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
  183. #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
  184. #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
  185. #define MACRO_NAND_DISABLE_CE(nandptr) do \
  186. { \
  187. switch((unsigned long)nandptr) \
  188. { \
  189. case CFG_NAND0_BASE: \
  190. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
  191. break; \
  192. case CFG_NAND1_BASE: \
  193. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
  194. break; \
  195. } \
  196. } while(0)
  197. #define MACRO_NAND_ENABLE_CE(nandptr) do \
  198. { \
  199. switch((unsigned long)nandptr) \
  200. { \
  201. case CFG_NAND0_BASE: \
  202. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
  203. break; \
  204. case CFG_NAND1_BASE: \
  205. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
  206. break; \
  207. } \
  208. } while(0)
  209. #define MACRO_NAND_CTL_CLRALE(nandptr) do \
  210. { \
  211. switch((unsigned long)nandptr) \
  212. { \
  213. case CFG_NAND0_BASE: \
  214. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
  215. break; \
  216. case CFG_NAND1_BASE: \
  217. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
  218. break; \
  219. } \
  220. } while(0)
  221. #define MACRO_NAND_CTL_SETALE(nandptr) do \
  222. { \
  223. switch((unsigned long)nandptr) \
  224. { \
  225. case CFG_NAND0_BASE: \
  226. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
  227. break; \
  228. case CFG_NAND1_BASE: \
  229. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
  230. break; \
  231. } \
  232. } while(0)
  233. #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
  234. { \
  235. switch((unsigned long)nandptr) \
  236. { \
  237. case CFG_NAND0_BASE: \
  238. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
  239. break; \
  240. case CFG_NAND1_BASE: \
  241. out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
  242. break; \
  243. } \
  244. } while(0)
  245. #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
  246. switch((unsigned long)nandptr) { \
  247. case CFG_NAND0_BASE: \
  248. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
  249. break; \
  250. case CFG_NAND1_BASE: \
  251. out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
  252. break; \
  253. } \
  254. } while(0)
  255. #ifdef NAND_NO_RB
  256. /* constant delay (see also tR in the datasheet) */
  257. #define NAND_WAIT_READY(nand) do { \
  258. udelay(12); \
  259. } while (0)
  260. #else
  261. /* use the R/B pin */
  262. /* TBD */
  263. #endif
  264. #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
  265. #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
  266. #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
  267. #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
  268. /*-----------------------------------------------------------------------
  269. * PCI stuff
  270. *-----------------------------------------------------------------------
  271. */
  272. #if 0 /* No PCI on CATcenter */
  273. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  274. #define PCI_HOST_FORCE 1 /* configure as pci host */
  275. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  276. #define CONFIG_PCI /* include pci support */
  277. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  278. #undef CONFIG_PCI_PNP /* do pci plug-and-play */
  279. /* resource configuration */
  280. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  281. #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
  282. #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
  283. #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  284. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  285. #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  286. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  287. #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
  288. #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  289. #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  290. #endif /* No PCI */
  291. /*-----------------------------------------------------------------------
  292. * Start addresses for the final memory configuration
  293. * (Set up by the startup code)
  294. * Please note that CFG_SDRAM_BASE _must_ start at 0
  295. */
  296. #define CFG_SDRAM_BASE 0x00000000
  297. #define CFG_FLASH_BASE 0xFFFC0000
  298. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  299. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  300. #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
  301. /*
  302. * For booting Linux, the board info and command line data
  303. * have to be in the first 8 MB of memory, since this is
  304. * the maximum mapped by the Linux kernel during initialization.
  305. */
  306. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  307. /*-----------------------------------------------------------------------
  308. * FLASH organization
  309. */
  310. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  311. #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  312. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  313. #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  314. #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  315. #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  316. #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  317. /*
  318. * The following defines are added for buggy IOP480 byte interface.
  319. * All other boards should use the standard values (CPCI405 etc.)
  320. */
  321. #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
  322. #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
  323. #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
  324. #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  325. /*-----------------------------------------------------------------------
  326. * Environment Variable setup
  327. */
  328. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  329. #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
  330. #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
  331. #define CFG_ENV_ADDR_REDUND 0xFFFFA000
  332. #define CFG_ENV_SIZE_REDUND 0x2000
  333. #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
  334. #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
  335. #define CFG_NVRAM_SIZE 242 /* NVRAM size */
  336. /*-----------------------------------------------------------------------
  337. * I2C EEPROM (CAT24WC16) for environment
  338. */
  339. #define CONFIG_HARD_I2C /* I2c with hardware support */
  340. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  341. #define CFG_I2C_SLAVE 0x7F
  342. #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  343. #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  344. /* mask of address bits that overflow into the "EEPROM chip address" */
  345. /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
  346. #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  347. /* 16 byte page write mode using*/
  348. /* last 4 bits of the address */
  349. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  350. #define CFG_EEPROM_PAGE_WRITE_ENABLE
  351. /*-----------------------------------------------------------------------
  352. * Cache Configuration
  353. */
  354. #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
  355. /* have only 8kB, 16kB is save here */
  356. #define CFG_CACHELINE_SIZE 32 /* ... */
  357. #if defined(CONFIG_CMD_KGDB)
  358. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  359. #endif
  360. /*
  361. * Init Memory Controller:
  362. *
  363. * BR0/1 and OR0/1 (FLASH)
  364. */
  365. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  366. /*-----------------------------------------------------------------------
  367. * External Bus Controller (EBC) Setup
  368. */
  369. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  370. #define CFG_EBC_PB0AP 0x92015480
  371. #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  372. /* Memory Bank 1 (External SRAM) initialization */
  373. /* Since this must replace NOR Flash, we use the same settings for CS0 */
  374. #define CFG_EBC_PB1AP 0x92015480
  375. #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
  376. /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
  377. #define CFG_EBC_PB2AP 0x92015480
  378. #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
  379. /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
  380. #define CFG_EBC_PB3AP 0x92015480
  381. #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
  382. #ifdef CONFIG_PPCHAMELEON_SMI712
  383. /*
  384. * Video console (graphic: SMI LynxEM)
  385. */
  386. #define CONFIG_VIDEO
  387. #define CONFIG_CFB_CONSOLE
  388. #define CONFIG_VIDEO_SMI_LYNXEM
  389. #define CONFIG_VIDEO_LOGO
  390. /*#define CONFIG_VIDEO_BMP_LOGO*/
  391. #define CONFIG_CONSOLE_EXTRA_INFO
  392. #define CONFIG_VGA_AS_SINGLE_DEVICE
  393. /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
  394. #define CFG_ISA_IO 0xE8000000
  395. /* see also drivers/video/videomodes.c */
  396. #define CFG_DEFAULT_VIDEO_MODE 0x303
  397. #endif
  398. /*-----------------------------------------------------------------------
  399. * FPGA stuff
  400. */
  401. /* FPGA internal regs */
  402. #define CFG_FPGA_MODE 0x00
  403. #define CFG_FPGA_STATUS 0x02
  404. #define CFG_FPGA_TS 0x04
  405. #define CFG_FPGA_TS_LOW 0x06
  406. #define CFG_FPGA_TS_CAP0 0x10
  407. #define CFG_FPGA_TS_CAP0_LOW 0x12
  408. #define CFG_FPGA_TS_CAP1 0x14
  409. #define CFG_FPGA_TS_CAP1_LOW 0x16
  410. #define CFG_FPGA_TS_CAP2 0x18
  411. #define CFG_FPGA_TS_CAP2_LOW 0x1a
  412. #define CFG_FPGA_TS_CAP3 0x1c
  413. #define CFG_FPGA_TS_CAP3_LOW 0x1e
  414. /* FPGA Mode Reg */
  415. #define CFG_FPGA_MODE_CF_RESET 0x0001
  416. #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
  417. #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
  418. #define CFG_FPGA_MODE_TS_CLEAR 0x2000
  419. /* FPGA Status Reg */
  420. #define CFG_FPGA_STATUS_DIP0 0x0001
  421. #define CFG_FPGA_STATUS_DIP1 0x0002
  422. #define CFG_FPGA_STATUS_DIP2 0x0004
  423. #define CFG_FPGA_STATUS_FLASH 0x0008
  424. #define CFG_FPGA_STATUS_TS_IRQ 0x1000
  425. #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  426. #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  427. /* FPGA program pin configuration */
  428. #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  429. #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  430. #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  431. #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  432. #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  433. /*-----------------------------------------------------------------------
  434. * Definitions for initial stack pointer and data area (in data cache)
  435. */
  436. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  437. #define CFG_TEMP_STACK_OCM 1
  438. /* On Chip Memory location */
  439. #define CFG_OCM_DATA_ADDR 0xF8000000
  440. #define CFG_OCM_DATA_SIZE 0x1000
  441. #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
  442. #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  443. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  444. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  445. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  446. /*-----------------------------------------------------------------------
  447. * Definitions for GPIO setup (PPC405EP specific)
  448. *
  449. * GPIO0[0] - External Bus Controller BLAST output
  450. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  451. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  452. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  453. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  454. * GPIO0[24-27] - UART0 control signal inputs/outputs
  455. * GPIO0[28-29] - UART1 data signal input/output
  456. * GPIO0[30] - EMAC0 input
  457. * GPIO0[31] - EMAC1 reject packet as output
  458. */
  459. #define CFG_GPIO0_OSRH 0x40000550
  460. #define CFG_GPIO0_OSRL 0x00000110
  461. #define CFG_GPIO0_ISR1H 0x00000000
  462. /*#define CFG_GPIO0_ISR1L 0x15555445*/
  463. #define CFG_GPIO0_ISR1L 0x15555444
  464. #define CFG_GPIO0_TSRH 0x00000000
  465. #define CFG_GPIO0_TSRL 0x00000000
  466. #define CFG_GPIO0_TCR 0xF7FF8014
  467. /*
  468. * Internal Definitions
  469. *
  470. * Boot Flags
  471. */
  472. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  473. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  474. #define CONFIG_NO_SERIAL_EEPROM
  475. /*--------------------------------------------------------------------*/
  476. #ifdef CONFIG_NO_SERIAL_EEPROM
  477. /*
  478. !-----------------------------------------------------------------------
  479. ! Defines for entry options.
  480. ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  481. ! are plugged in the board will be utilized as non-ECC DIMMs.
  482. !-----------------------------------------------------------------------
  483. */
  484. #undef AUTO_MEMORY_CONFIG
  485. #define DIMM_READ_ADDR 0xAB
  486. #define DIMM_WRITE_ADDR 0xAA
  487. #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
  488. #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
  489. #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
  490. #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
  491. #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
  492. #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
  493. #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
  494. #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
  495. #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
  496. #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
  497. /* Defines for CPC0_PLLMR1 Register fields */
  498. #define PLL_ACTIVE 0x80000000
  499. #define CPC0_PLLMR1_SSCS 0x80000000
  500. #define PLL_RESET 0x40000000
  501. #define CPC0_PLLMR1_PLLR 0x40000000
  502. /* Feedback multiplier */
  503. #define PLL_FBKDIV 0x00F00000
  504. #define CPC0_PLLMR1_FBDV 0x00F00000
  505. #define PLL_FBKDIV_16 0x00000000
  506. #define PLL_FBKDIV_1 0x00100000
  507. #define PLL_FBKDIV_2 0x00200000
  508. #define PLL_FBKDIV_3 0x00300000
  509. #define PLL_FBKDIV_4 0x00400000
  510. #define PLL_FBKDIV_5 0x00500000
  511. #define PLL_FBKDIV_6 0x00600000
  512. #define PLL_FBKDIV_7 0x00700000
  513. #define PLL_FBKDIV_8 0x00800000
  514. #define PLL_FBKDIV_9 0x00900000
  515. #define PLL_FBKDIV_10 0x00A00000
  516. #define PLL_FBKDIV_11 0x00B00000
  517. #define PLL_FBKDIV_12 0x00C00000
  518. #define PLL_FBKDIV_13 0x00D00000
  519. #define PLL_FBKDIV_14 0x00E00000
  520. #define PLL_FBKDIV_15 0x00F00000
  521. /* Forward A divisor */
  522. #define PLL_FWDDIVA 0x00070000
  523. #define CPC0_PLLMR1_FWDVA 0x00070000
  524. #define PLL_FWDDIVA_8 0x00000000
  525. #define PLL_FWDDIVA_7 0x00010000
  526. #define PLL_FWDDIVA_6 0x00020000
  527. #define PLL_FWDDIVA_5 0x00030000
  528. #define PLL_FWDDIVA_4 0x00040000
  529. #define PLL_FWDDIVA_3 0x00050000
  530. #define PLL_FWDDIVA_2 0x00060000
  531. #define PLL_FWDDIVA_1 0x00070000
  532. /* Forward B divisor */
  533. #define PLL_FWDDIVB 0x00007000
  534. #define CPC0_PLLMR1_FWDVB 0x00007000
  535. #define PLL_FWDDIVB_8 0x00000000
  536. #define PLL_FWDDIVB_7 0x00001000
  537. #define PLL_FWDDIVB_6 0x00002000
  538. #define PLL_FWDDIVB_5 0x00003000
  539. #define PLL_FWDDIVB_4 0x00004000
  540. #define PLL_FWDDIVB_3 0x00005000
  541. #define PLL_FWDDIVB_2 0x00006000
  542. #define PLL_FWDDIVB_1 0x00007000
  543. /* PLL tune bits */
  544. #define PLL_TUNE_MASK 0x000003FF
  545. #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
  546. #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
  547. #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
  548. #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
  549. #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
  550. #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
  551. #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
  552. /* Defines for CPC0_PLLMR0 Register fields */
  553. /* CPU divisor */
  554. #define PLL_CPUDIV 0x00300000
  555. #define CPC0_PLLMR0_CCDV 0x00300000
  556. #define PLL_CPUDIV_1 0x00000000
  557. #define PLL_CPUDIV_2 0x00100000
  558. #define PLL_CPUDIV_3 0x00200000
  559. #define PLL_CPUDIV_4 0x00300000
  560. /* PLB divisor */
  561. #define PLL_PLBDIV 0x00030000
  562. #define CPC0_PLLMR0_CBDV 0x00030000
  563. #define PLL_PLBDIV_1 0x00000000
  564. #define PLL_PLBDIV_2 0x00010000
  565. #define PLL_PLBDIV_3 0x00020000
  566. #define PLL_PLBDIV_4 0x00030000
  567. /* OPB divisor */
  568. #define PLL_OPBDIV 0x00003000
  569. #define CPC0_PLLMR0_OPDV 0x00003000
  570. #define PLL_OPBDIV_1 0x00000000
  571. #define PLL_OPBDIV_2 0x00001000
  572. #define PLL_OPBDIV_3 0x00002000
  573. #define PLL_OPBDIV_4 0x00003000
  574. /* EBC divisor */
  575. #define PLL_EXTBUSDIV 0x00000300
  576. #define CPC0_PLLMR0_EPDV 0x00000300
  577. #define PLL_EXTBUSDIV_2 0x00000000
  578. #define PLL_EXTBUSDIV_3 0x00000100
  579. #define PLL_EXTBUSDIV_4 0x00000200
  580. #define PLL_EXTBUSDIV_5 0x00000300
  581. /* MAL divisor */
  582. #define PLL_MALDIV 0x00000030
  583. #define CPC0_PLLMR0_MPDV 0x00000030
  584. #define PLL_MALDIV_1 0x00000000
  585. #define PLL_MALDIV_2 0x00000010
  586. #define PLL_MALDIV_3 0x00000020
  587. #define PLL_MALDIV_4 0x00000030
  588. /* PCI divisor */
  589. #define PLL_PCIDIV 0x00000003
  590. #define CPC0_PLLMR0_PPFD 0x00000003
  591. #define PLL_PCIDIV_1 0x00000000
  592. #define PLL_PCIDIV_2 0x00000001
  593. #define PLL_PCIDIV_3 0x00000002
  594. #define PLL_PCIDIV_4 0x00000003
  595. #ifdef CONFIG_PPCHAMELEON_CLK_25
  596. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
  597. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  598. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  599. PLL_MALDIV_1 | PLL_PCIDIV_4)
  600. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
  601. PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
  602. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  603. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  604. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  605. PLL_MALDIV_1 | PLL_PCIDIV_4)
  606. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
  607. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  608. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  609. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  610. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  611. PLL_MALDIV_1 | PLL_PCIDIV_4)
  612. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  613. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  614. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  615. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  616. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  617. PLL_MALDIV_1 | PLL_PCIDIV_2)
  618. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  619. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  620. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  621. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  622. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
  623. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  624. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  625. PLL_MALDIV_1 | PLL_PCIDIV_4)
  626. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
  627. PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
  628. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  629. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  630. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  631. PLL_MALDIV_1 | PLL_PCIDIV_4)
  632. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
  633. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  634. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  635. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  636. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  637. PLL_MALDIV_1 | PLL_PCIDIV_4)
  638. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  639. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  640. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  641. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  642. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  643. PLL_MALDIV_1 | PLL_PCIDIV_2)
  644. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  645. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  646. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  647. #else
  648. #error "* External frequency (SysClk) not defined! *"
  649. #endif
  650. #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
  651. /* Model HI */
  652. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
  653. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
  654. #define CFG_OPB_FREQ 55555555
  655. /* Model ME */
  656. #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
  657. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
  658. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
  659. #define CFG_OPB_FREQ 66666666
  660. #else
  661. /* Model BA (default) */
  662. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
  663. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
  664. #define CFG_OPB_FREQ 66666666
  665. #endif
  666. #endif /* CONFIG_NO_SERIAL_EEPROM */
  667. #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
  668. #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
  669. /*
  670. * JFFS2 partitions
  671. *
  672. */
  673. /* No command line, one static partition */
  674. #undef CONFIG_JFFS2_CMDLINE
  675. #define CONFIG_JFFS2_DEV "nand"
  676. #define CONFIG_JFFS2_PART_SIZE 0x00200000
  677. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  678. /* mtdparts command line support
  679. *
  680. * Note: fake mtd_id used, no linux mtd map file
  681. */
  682. /*
  683. #define CONFIG_JFFS2_CMDLINE
  684. #define MTDIDS_DEFAULT "nand0=catcenter"
  685. #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
  686. */
  687. #endif /* __CONFIG_H */