Alaska8220.h 9.5 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /*
  26. * High Level Configuration Options
  27. * (easy to change)
  28. */
  29. #define CONFIG_MPC8220 1
  30. #define CONFIG_ALASKA8220 1 /* ... on Alaska board */
  31. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  32. /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  33. determine the CPU speed. */
  34. #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
  35. #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
  36. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  37. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  38. /*
  39. * Serial console configuration
  40. */
  41. /* Define this for PSC console
  42. #define CONFIG_PSC_CONSOLE 1
  43. */
  44. #define CONFIG_EXTUART_CONSOLE 1
  45. #ifdef CONFIG_EXTUART_CONSOLE
  46. # define CONFIG_CONS_INDEX 1
  47. # define CFG_NS16550_SERIAL
  48. # define CFG_NS16550
  49. # define CFG_NS16550_REG_SIZE 1
  50. # define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
  51. # define CFG_NS16550_CLK 18432000
  52. #endif
  53. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  54. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  55. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  56. /*
  57. * BOOTP options
  58. */
  59. #define CONFIG_BOOTP_BOOTFILESIZE
  60. #define CONFIG_BOOTP_BOOTPATH
  61. #define CONFIG_BOOTP_GATEWAY
  62. #define CONFIG_BOOTP_HOSTNAME
  63. /*
  64. * Command line configuration.
  65. */
  66. #include <config_cmd_default.h>
  67. #define CONFIG_CMD_BOOTD
  68. #define CONFIG_CMD_CACHE
  69. #define CONFIG_CMD_DHCP
  70. #define CONFIG_CMD_DIAG
  71. #define CONFIG_CMD_EEPROM
  72. #define CONFIG_CMD_ELF
  73. #define CONFIG_CMD_I2C
  74. #define CONFIG_CMD_NET
  75. #define CONFIG_CMD_NFS
  76. #define CONFIG_CMD_PCI
  77. #define CONFIG_CMD_PING
  78. #define CONFIG_CMD_REGINFO
  79. #define CONFIG_CMD_SDRAM
  80. #define CONFIG_CMD_SNTP
  81. #define CONFIG_NET_MULTI
  82. #define CONFIG_MII
  83. /*
  84. * Autobooting
  85. */
  86. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  87. #define CONFIG_BOOTARGS "root=/dev/ram rw"
  88. #define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
  89. #define CONFIG_HAS_ETH1
  90. #define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
  91. #define CONFIG_IPADDR 192.162.1.2
  92. #define CONFIG_NETMASK 255.255.255.0
  93. #define CONFIG_SERVERIP 192.162.1.1
  94. #define CONFIG_GATEWAYIP 192.162.1.1
  95. #define CONFIG_HOSTNAME Alaska
  96. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  97. /*
  98. * I2C configuration
  99. */
  100. #define CONFIG_HARD_I2C 1
  101. #define CFG_I2C_MODULE 1
  102. #define CFG_I2C_SPEED 100000 /* 100 kHz */
  103. #define CFG_I2C_SLAVE 0x7F
  104. /*
  105. * EEPROM configuration
  106. */
  107. #define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
  108. #define CFG_I2C_EEPROM_ADDR_LEN 1
  109. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  110. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
  111. /*
  112. #define CONFIG_ENV_IS_IN_EEPROM 1
  113. #define CFG_ENV_OFFSET 0
  114. #define CFG_ENV_SIZE 256
  115. */
  116. /* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
  117. else undefined it will boot from Intel Strata flash */
  118. #define CFG_AMD_BOOT 1
  119. /*
  120. * Flexbus Chipselect configuration
  121. */
  122. #if defined (CFG_AMD_BOOT)
  123. #define CFG_CS0_BASE 0xfff0
  124. #define CFG_CS0_MASK 0x00080000 /* 512 KB */
  125. #define CFG_CS0_CTRL 0x003f0d40
  126. #define CFG_CS1_BASE 0xfe00
  127. #define CFG_CS1_MASK 0x01000000 /* 16 MB */
  128. #define CFG_CS1_CTRL 0x003f1540
  129. #else
  130. #define CFG_CS0_BASE 0xff00
  131. #define CFG_CS0_MASK 0x01000000 /* 16 MB */
  132. #define CFG_CS0_CTRL 0x003f1540
  133. #define CFG_CS1_BASE 0xfe08
  134. #define CFG_CS1_MASK 0x00080000 /* 512 KB */
  135. #define CFG_CS1_CTRL 0x003f0d40
  136. #endif
  137. #define CFG_CS2_BASE 0xf100
  138. #define CFG_CS2_MASK 0x00040000
  139. #define CFG_CS2_CTRL 0x003f1140
  140. #define CFG_CS3_BASE 0xf200
  141. #define CFG_CS3_MASK 0x00040000
  142. #define CFG_CS3_CTRL 0x003f1100
  143. #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
  144. #define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
  145. #if defined (CFG_AMD_BOOT)
  146. #define CFG_AMD_BASE CFG_FLASH0_BASE
  147. #define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
  148. #define CFG_FLASH_BASE CFG_AMD_BASE
  149. #else
  150. #define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
  151. #define CFG_AMD_BASE CFG_FLASH1_BASE
  152. #define CFG_FLASH_BASE CFG_INTEL_BASE
  153. #endif
  154. #define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
  155. #define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
  156. #define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
  157. #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
  158. #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  159. #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  160. #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
  161. #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  162. #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  163. #define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
  164. #define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
  165. #define CFG_FLASH_CHECKSUM
  166. /*
  167. * Environment settings
  168. */
  169. #define CONFIG_ENV_IS_IN_FLASH 1
  170. #if defined (CFG_AMD_BOOT)
  171. #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
  172. #define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
  173. #define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
  174. #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
  175. #define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
  176. #define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
  177. #else
  178. #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
  179. #define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
  180. #define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
  181. #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
  182. #define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
  183. #define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
  184. #endif
  185. #define CONFIG_ENV_OVERWRITE 1
  186. #if defined CONFIG_ENV_IS_IN_FLASH
  187. #undef CONFIG_ENV_IS_IN_NVRAM
  188. #undef CONFIG_ENV_IS_IN_EEPROM
  189. #elif defined CONFIG_ENV_IS_IN_NVRAM
  190. #undef CONFIG_ENV_IS_IN_FLASH
  191. #undef CONFIG_ENV_IS_IN_EEPROM
  192. #elif defined CONFIG_ENV_IS_IN_EEPROM
  193. #undef CONFIG_ENV_IS_IN_NVRAM
  194. #undef CONFIG_ENV_IS_IN_FLASH
  195. #endif
  196. /*
  197. * Memory map
  198. */
  199. #define CFG_MBAR 0xF0000000
  200. #define CFG_SDRAM_BASE 0x00000000
  201. #define CFG_DEFAULT_MBAR 0x80000000
  202. #define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
  203. #define CFG_SRAM_SIZE 0x8000
  204. /* Use SRAM until RAM will be available */
  205. #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
  206. #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
  207. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  208. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  209. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  210. #define CFG_MONITOR_BASE TEXT_BASE
  211. #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  212. # define CFG_RAMBOOT 1
  213. #endif
  214. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  215. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  216. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  217. /* SDRAM configuration */
  218. #define CFG_SDRAM_TOTAL_BANKS 2
  219. #define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
  220. #define CFG_SDRAM_SPD_SIZE 0x40
  221. #define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
  222. /* SDRAM drive strength register */
  223. #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
  224. (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
  225. (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
  226. (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
  227. (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
  228. /*
  229. * Ethernet configuration
  230. */
  231. #define CONFIG_MPC8220_FEC 1
  232. #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
  233. #define CONFIG_PHY_ADDR 0x18
  234. /*
  235. * Miscellaneous configurable options
  236. */
  237. #define CFG_LONGHELP /* undef to save memory */
  238. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  239. #if defined(CONFIG_CMD_KGDB)
  240. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  241. #else
  242. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  243. #endif
  244. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  245. #define CFG_MAXARGS 16 /* max number of command args */
  246. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  247. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  248. #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  249. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  250. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  251. #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
  252. #if defined(CONFIG_CMD_KGDB)
  253. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  254. #endif
  255. /*
  256. * Various low-level settings
  257. */
  258. #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
  259. #define CFG_HID0_FINAL HID0_ICE
  260. /*
  261. * JFFS2 partitions
  262. */
  263. /* No command line, one static partition */
  264. /*
  265. #undef CONFIG_JFFS2_CMDLINE
  266. #define CONFIG_JFFS2_DEV "nor0"
  267. #define CONFIG_JFFS2_PART_SIZE 0x00400000
  268. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  269. */
  270. /* mtdparts command line support */
  271. /*
  272. #define CONFIG_JFFS2_CMDLINE
  273. #define MTDIDS_DEFAULT "nor0=alaska-0"
  274. #define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
  275. */
  276. #endif /* __CONFIG_H */