Adder.h 7.1 KB

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  1. /*
  2. * Copyright (C) 2004-2005 Arabella Software Ltd.
  3. * Yuli Barcohen <yuli@arabellasw.com>
  4. *
  5. * Support for Analogue&Micro Adder boards family.
  6. * Tested on AdderII and Adder87x.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
  29. #define CONFIG_MPC875
  30. #endif
  31. #define CONFIG_ADDER /* Analogue&Micro Adder board */
  32. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  33. #define CONFIG_BAUDRATE 38400
  34. #define CONFIG_ETHER_ON_FEC1
  35. #define CONFIG_ETHER_ON_FEC2
  36. #define CONFIG_HAS_ETH0
  37. #define CONFIG_HAS_ETH1
  38. #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
  39. #define CFG_DISCOVER_PHY
  40. #define CONFIG_MII_INIT 1
  41. #define FEC_ENET
  42. #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
  43. #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
  44. #define CONFIG_8xx_CPUCLK_DEFAULT 50000000
  45. #define CFG_8xx_CPUCLK_MIN 40000000
  46. #ifdef CONFIG_MPC852T
  47. #define CFG_8xx_CPUCLK_MAX 50000000
  48. #else
  49. #define CFG_8xx_CPUCLK_MAX 133000000
  50. #endif /* CONFIG_MPC852T */
  51. /*
  52. * BOOTP options
  53. */
  54. #define CONFIG_BOOTP_BOOTFILESIZE
  55. #define CONFIG_BOOTP_BOOTPATH
  56. #define CONFIG_BOOTP_GATEWAY
  57. #define CONFIG_BOOTP_HOSTNAME
  58. /*
  59. * Command line configuration.
  60. */
  61. #include <config_cmd_default.h>
  62. #define CONFIG_CMD_DHCP
  63. #define CONFIG_CMD_IMMAP
  64. #define CONFIG_CMD_MII
  65. #define CONFIG_CMD_PING
  66. #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
  67. #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
  68. #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
  69. #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
  70. #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
  71. /*-----------------------------------------------------------------------
  72. * Miscellaneous configurable options
  73. */
  74. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  75. #define CFG_HUSH_PARSER
  76. #define CFG_PROMPT_HUSH_PS2 "> "
  77. #define CFG_LONGHELP /* #undef to save memory */
  78. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  79. #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
  80. #define CFG_MAXARGS 16 /* Max number of command args */
  81. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  82. #define CFG_LOAD_ADDR 0x400000 /* Default load address */
  83. #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
  84. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  85. /*-----------------------------------------------------------------------
  86. * RAM configuration (note that CFG_SDRAM_BASE must be zero)
  87. */
  88. #define CFG_SDRAM_BASE 0x00000000
  89. #define CFG_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
  90. #define CFG_MAMR 0x00002114
  91. /*
  92. * 4096 Up to 4096 SDRAM rows
  93. * 1000 factor s -> ms
  94. * 32 PTP (pre-divider from MPTPR)
  95. * 4 Number of refresh cycles per period
  96. * 64 Refresh cycle in ms per number of rows
  97. */
  98. #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
  99. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  100. #define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
  101. #define CFG_RESET_ADDRESS 0x09900000
  102. /*-----------------------------------------------------------------------
  103. * For booting Linux, the board info and command line data
  104. * have to be in the first 8 MB of memory, since this is
  105. * the maximum mapped by the Linux kernel during initialization.
  106. */
  107. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  108. #define CFG_MONITOR_BASE TEXT_BASE
  109. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
  110. #ifdef CONFIG_BZIP2
  111. #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
  112. #else
  113. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
  114. #endif /* CONFIG_BZIP2 */
  115. /*-----------------------------------------------------------------------
  116. * Flash organisation
  117. */
  118. #define CFG_FLASH_BASE 0xFE000000
  119. #define CFG_FLASH_CFI /* The flash is CFI compatible */
  120. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  121. #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  122. #define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
  123. /* Environment is in flash */
  124. #define CONFIG_ENV_IS_IN_FLASH
  125. #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
  126. #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  127. #define CONFIG_ENV_OVERWRITE
  128. #define CFG_OR0_PRELIM 0xFF000774
  129. #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
  130. #define CFG_DIRECT_FLASH_TFTP
  131. /*-----------------------------------------------------------------------
  132. * Internal Memory Map Register
  133. */
  134. #define CFG_IMMR 0xFF000000
  135. /*-----------------------------------------------------------------------
  136. * Definitions for initial stack pointer and data area (in DPRAM)
  137. */
  138. #define CFG_INIT_RAM_ADDR CFG_IMMR
  139. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  140. #define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
  141. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  142. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  143. /*-----------------------------------------------------------------------
  144. * Configuration registers
  145. */
  146. #ifdef CONFIG_WATCHDOG
  147. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
  148. SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
  149. SYPCR_SWP)
  150. #else
  151. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
  152. SYPCR_SWF | SYPCR_SWP)
  153. #endif /* CONFIG_WATCHDOG */
  154. #define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
  155. /* TBSCR - Time Base Status and Control Register */
  156. #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
  157. /* PISCR - Periodic Interrupt Status and Control */
  158. #define CFG_PISCR (PISCR_PS | PISCR_PITF)
  159. /* PLPRCR - PLL, Low-Power, and Reset Control Register */
  160. /* #define CFG_PLPRCR PLPRCR_TEXPS */
  161. /* SCCR - System Clock and reset Control Register */
  162. #define SCCR_MASK SCCR_EBDF11
  163. #define CFG_SCCR SCCR_RTSEL
  164. #define CFG_DER 0
  165. /*-----------------------------------------------------------------------
  166. * Cache Configuration
  167. */
  168. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
  169. /*-----------------------------------------------------------------------
  170. * Internal Definitions
  171. *
  172. * Boot Flags
  173. */
  174. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
  175. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  176. /* pass open firmware flat tree */
  177. #define CONFIG_OF_LIBFDT 1
  178. #define CONFIG_OF_BOARD_SETUP 1
  179. #endif /* __CONFIG_H */