ATUM8548.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459
  1. /*
  2. * Copyright 2007
  3. * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
  4. *
  5. * Copyright 2004, 2007 Freescale Semiconductor.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * atum8548 board configuration file
  27. *
  28. * Please refer to doc/README.atum8548 for more info.
  29. *
  30. */
  31. #ifndef __CONFIG_H
  32. #define __CONFIG_H
  33. /* Debug Options, Disable in production
  34. #define ET_DEBUG 1
  35. #define CONFIG_PANIC_HANG 1
  36. #define DEBUG 1
  37. */
  38. /* CPLD Configuration Options */
  39. #define MPC85xx_ATUM_CLKOCR 0x80000002
  40. /* High Level Configuration Options */
  41. #define CONFIG_BOOKE 1 /* BOOKE */
  42. #define CONFIG_E500 1 /* BOOKE e500 family */
  43. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  44. #define CONFIG_MPC8548 1 /* MPC8548 specific */
  45. #define CONFIG_PCI 1 /* enable any pci type devices */
  46. #define CONFIG_PCI1 1 /* PCI controller 1 */
  47. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  48. #define CONFIG_PCI2 1 /* PCI controller 2 */
  49. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  50. #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
  51. #define CONFIG_ENV_OVERWRITE
  52. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  53. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  54. #define CONFIG_SYS_CLK_FREQ 33000000
  55. /*
  56. * These can be toggled for performance analysis, otherwise use default.
  57. */
  58. #define CONFIG_L2_CACHE /* toggle L2 cache */
  59. #define CONFIG_BTB /* toggle branch predition */
  60. #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
  61. #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
  62. /*
  63. * Only possible on E500 Version 2 or newer cores.
  64. */
  65. #define CONFIG_ENABLE_36BIT_PHYS 1
  66. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  67. #define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
  68. #define CONFIG_ENABLE_36BIT_PHYS 1
  69. #undef CFG_DRAM_TEST
  70. #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
  71. #define CFG_MEMTEST_END 0x00400000
  72. /*
  73. * Base addresses -- Note these are effective addresses where the
  74. * actual resources get mapped (not physical addresses)
  75. */
  76. #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  77. #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  78. #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
  79. #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
  80. #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
  81. #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
  82. #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
  83. #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
  84. /* DDR Setup */
  85. #define CONFIG_FSL_DDR2
  86. #undef CONFIG_FSL_DDR_INTERACTIVE
  87. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  88. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  89. #define CONFIG_DDR_SPD
  90. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  91. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  92. #define CFG_DDR_SDRAM_BASE 0x00000000
  93. #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
  94. #define CONFIG_VERY_BIG_RAM
  95. #define CONFIG_NUM_DDR_CONTROLLERS 1
  96. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  97. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  98. /* I2C addresses of SPD EEPROMs */
  99. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  100. /* Manually set up DDR parameters */
  101. #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
  102. #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
  103. #define CFG_DDR_CS0_CONFIG 0x80000102
  104. #define CFG_DDR_TIMING_0 0x00260802
  105. #define CFG_DDR_TIMING_1 0x38355322
  106. #define CFG_DDR_TIMING_2 0x039048c7
  107. #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  108. #define CFG_DDR_MODE 0x00000432
  109. #define CFG_DDR_INTERVAL 0x05150100
  110. #define DDR_SDRAM_CFG 0x43000000
  111. #undef CONFIG_CLOCKS_IN_MHZ
  112. /*
  113. * Local Bus Definitions
  114. */
  115. /*
  116. * FLASH on the Local Bus
  117. * based on flash chip S29GL01GP
  118. * One bank, 128M, using the CFI driver.
  119. * Boot from BR0 bank at 0xf800_0000
  120. *
  121. * BR0:
  122. * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
  123. * Port Size = 16 bits = BRx[19:20] = 10
  124. * Use GPCM = BRx[24:26] = 000
  125. * Valid = BRx[31] = 1
  126. *
  127. * 0 4 8 12 16 20 24 28
  128. * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
  129. *
  130. * OR0:
  131. * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
  132. * Reserved ORx[17:18] = 00
  133. * CSNT = ORx[20] = 1
  134. * ACS = half cycle delay = ORx[21:22] = 11
  135. * SCY = 6 = ORx[24:27] = 0110
  136. * TRLX = use relaxed timing = ORx[29] = 1
  137. * EAD = use external address latch delay = OR[31] = 1
  138. *
  139. * 0 4 8 12 16 20 24 28
  140. * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
  141. */
  142. #define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
  143. #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
  144. #define CFG_BR0_PRELIM 0xf8001001
  145. #define CFG_OR0_PRELIM 0xf8000E65
  146. #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  147. #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
  148. #undef CFG_FLASH_CHECKSUM
  149. #define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
  150. #define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
  151. #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  152. #define CONFIG_FLASH_CFI_DRIVER 1
  153. #define CFG_FLASH_CFI 1
  154. #define CFG_FLASH_EMPTY_INFO
  155. /*
  156. * Flash on the LocalBus
  157. */
  158. #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
  159. /* Memory */
  160. #define CFG_INIT_RAM_LOCK 1
  161. #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  162. #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
  163. #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
  164. #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  165. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  166. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  167. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  168. #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  169. /* Serial Port */
  170. #define CONFIG_CONS_INDEX 1
  171. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  172. #define CFG_NS16550
  173. #define CFG_NS16550_SERIAL
  174. #define CFG_NS16550_REG_SIZE 1
  175. #define CFG_NS16550_CLK get_bus_freq(0)
  176. #define CFG_BAUDRATE_TABLE \
  177. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  178. #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
  179. #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
  180. /* Use the HUSH parser */
  181. #define CFG_HUSH_PARSER
  182. #ifdef CFG_HUSH_PARSER
  183. #define CFG_PROMPT_HUSH_PS2 "> "
  184. #endif
  185. /* pass open firmware flat tree */
  186. #define CONFIG_OF_LIBFDT 1
  187. #define CONFIG_OF_BOARD_SETUP 1
  188. /*
  189. * I2C
  190. */
  191. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  192. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  193. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  194. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  195. #define CFG_I2C_EEPROM_ADDR 0x57
  196. #define CFG_I2C_SLAVE 0x7F
  197. #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  198. #define CFG_I2C_OFFSET 0x3000
  199. /*
  200. * General PCI
  201. * Memory space is mapped 1-1, but I/O space must start from 0.
  202. */
  203. #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  204. #define CFG_PCI1_MEM_BASE 0x80000000
  205. #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  206. #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  207. #define CFG_PCI1_IO_BASE 0x00000000
  208. #define CFG_PCI1_IO_PHYS 0xe2000000
  209. #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
  210. #ifdef CONFIG_PCI2
  211. #define CFG_PCI2_MEM_BASE 0xC0000000
  212. #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
  213. #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
  214. #define CFG_PCI2_IO_BASE 0x00000000
  215. #define CFG_PCI2_IO_PHYS 0xe2800000
  216. #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
  217. #endif
  218. #ifdef CONFIG_PCIE1
  219. #define CFG_PCIE1_MEM_BASE 0xa0000000
  220. #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
  221. #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  222. #define CFG_PCIE1_IO_BASE 0x00000000
  223. #define CFG_PCIE1_IO_PHYS 0xe3000000
  224. #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
  225. #endif
  226. #if !defined(CONFIG_PCI_PNP)
  227. #define PCI_ENET0_IOADDR 0xe0000000
  228. #define PCI_ENET0_MEMADDR 0xe0000000
  229. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  230. #endif
  231. #if defined(CONFIG_PCI)
  232. #define CONFIG_NET_MULTI
  233. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  234. #undef CONFIG_EEPRO100
  235. #undef CONFIG_TULIP
  236. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  237. /* PCI view of System Memory */
  238. #define CFG_PCI_MEMORY_BUS 0x00000000
  239. #define CFG_PCI_MEMORY_PHYS 0x00000000
  240. #define CFG_PCI_MEMORY_SIZE 0x80000000
  241. #endif /* CONFIG_PCI */
  242. #if defined(CONFIG_TSEC_ENET)
  243. #ifndef CONFIG_NET_MULTI
  244. #define CONFIG_NET_MULTI 1
  245. #endif
  246. #define CONFIG_MII 1 /* MII PHY management */
  247. #define CONFIG_TSEC1 1
  248. #define CONFIG_TSEC1_NAME "eTSEC0"
  249. #define CONFIG_TSEC2 1
  250. #define CONFIG_TSEC2_NAME "eTSEC1"
  251. #define CONFIG_TSEC3 1
  252. #define CONFIG_TSEC3_NAME "eTSEC2"
  253. #define CONFIG_TSEC4 1
  254. #define CONFIG_TSEC4_NAME "eTSEC3"
  255. #undef CONFIG_MPC85XX_FEC
  256. #define TSEC1_PHY_ADDR 0
  257. #define TSEC2_PHY_ADDR 1
  258. #define TSEC3_PHY_ADDR 2
  259. #define TSEC4_PHY_ADDR 3
  260. #define TSEC1_PHYIDX 0
  261. #define TSEC2_PHYIDX 0
  262. #define TSEC3_PHYIDX 0
  263. #define TSEC4_PHYIDX 0
  264. #define TSEC1_FLAGS TSEC_GIGABIT
  265. #define TSEC2_FLAGS TSEC_GIGABIT
  266. #define TSEC3_FLAGS TSEC_GIGABIT
  267. #define TSEC4_FLAGS TSEC_GIGABIT
  268. /* Options are: eTSEC[0-3] */
  269. #define CONFIG_ETHPRIME "eTSEC2"
  270. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  271. #endif /* CONFIG_TSEC_ENET */
  272. /*
  273. * Environment
  274. */
  275. #define CONFIG_ENV_IS_IN_FLASH 1
  276. #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
  277. #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  278. #define CFG_ENV_SIZE 0x2000
  279. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  280. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  281. /*
  282. * BOOTP options
  283. */
  284. #define CONFIG_BOOTP_BOOTFILESIZE
  285. #define CONFIG_BOOTP_BOOTPATH
  286. #define CONFIG_BOOTP_GATEWAY
  287. #define CONFIG_BOOTP_HOSTNAME
  288. /*
  289. * Command line configuration.
  290. */
  291. #include <config_cmd_default.h>
  292. #define CONFIG_CMD_PING
  293. #define CONFIG_CMD_I2C
  294. #define CONFIG_CMD_MII
  295. #if defined(CONFIG_PCI)
  296. #define CONFIG_CMD_PCI
  297. #endif
  298. #undef CONFIG_WATCHDOG /* watchdog disabled */
  299. /*
  300. * Miscellaneous configurable options
  301. */
  302. #define CFG_LONGHELP /* undef to save memory */
  303. #define CFG_LOAD_ADDR 0x2000000 /* default load address */
  304. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  305. #if defined(CONFIG_CMD_KGDB)
  306. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  307. #else
  308. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  309. #endif
  310. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  311. #define CFG_MAXARGS 16 /* max number of command args */
  312. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  313. #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
  314. /*
  315. * For booting Linux, the board info and command line data
  316. * have to be in the first 8 MB of memory, since this is
  317. * the maximum mapped by the Linux kernel during initialization.
  318. */
  319. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  320. /*
  321. * Internal Definitions
  322. *
  323. * Boot Flags
  324. */
  325. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  326. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  327. #if defined(CONFIG_CMD_KGDB)
  328. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  329. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  330. #endif
  331. /*
  332. * Environment Configuration
  333. */
  334. /* The mac addresses for all ethernet interface */
  335. #if defined(CONFIG_TSEC_ENET)
  336. #define CONFIG_HAS_ETH0
  337. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  338. #define CONFIG_HAS_ETH1
  339. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  340. #define CONFIG_HAS_ETH2
  341. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  342. #define CONFIG_HAS_ETH3
  343. #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
  344. #endif
  345. #define CONFIG_IPADDR 10.101.43.142
  346. #define CONFIG_HOSTNAME atum
  347. #define CONFIG_ROOTPATH /nfsroot
  348. #define CONFIG_BOOTFILE /tftpboot/uImage.atum
  349. #define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
  350. #define CONFIG_SERVERIP 10.101.43.10
  351. #define CONFIG_GATEWAYIP 10.101.45.1
  352. #define CONFIG_NETMASK 255.255.248.0
  353. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  354. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  355. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  356. #define CONFIG_BAUDRATE 115200
  357. #define CONFIG_NFSBOOTCOMMAND \
  358. "setenv bootargs root=/dev/nfs rw " \
  359. "nfsroot=$serverip:$rootpath " \
  360. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  361. "console=$consoledev,$baudrate $othbootargs;" \
  362. "tftp $loadaddr $bootfile;" \
  363. "tftp $dtbaddr $dtbfile;" \
  364. "bootm $loadaddr - $dtbaddr"
  365. #define CONFIG_RAMBOOTCOMMAND \
  366. "setenv bootargs root=/dev/ram rw " \
  367. "console=$consoledev,$baudrate $othbootargs;" \
  368. "tftp $ramdiskaddr $ramdiskfile;" \
  369. "tftp $loadaddr $bootfile;" \
  370. "tftp $dtbaddr $dtbfile;" \
  371. "bootm $loadaddr $ramdiskaddr $dtbaddr"
  372. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  373. #endif /* __CONFIG_H */